functional verification test 中文意思是什麼

functional verification test 解釋
功能驗證測試
  • functional : adj 1 官能的，機能的。2 在起作用的；職務上的。3 【數學】函數的。4 【建築】從使用的觀點設計[構成]...
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  • test : n 1 檢驗，檢查；考查；測驗；考試；考驗。2 檢驗用品；試金石；【化學】試藥；（判斷的）標準。3 【化...
  1. ; measurement of vibration immission - part 3 : test calibration and assessment of the vibration measuring instrumentation ; primary test, verification, intermediate test, functional check in situ

    振動干擾測量.第3部分:測量儀器振動試驗
  2. It discusses the architecture of testbench in functional verification of dtv chip and detailed accounts realization of memory bist ( build in self test ) method

    本章介紹了各種主流驗證測試方法，著重敘述了dtv晶元中功能驗證的平臺結構設計和存儲器內建式自測試（ bist ）的具體實現。
  3. Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products

    討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。
  4. It has been an exigent task to reduce the difficulty of functional verification, cutting down the ratio of verification in the whole design duration, while assuring the coverage of functional verification when designing a high performance processor to solve this problem, the concept of random instruction testing has been introduced here. thus not only a lot of verification engineers " burdens of hand writing test is reduced, but also the influence of man - made factor in the process of testing

    如何在保證效果的同時，降低驗證工作的難度，減少驗證在整個設計周期的比率，已經成為高性能嵌入式處理器設計所迫切需要解決的一個問題。為了解決這個問題，引入了隨機指令測試的概念。這樣一來就可以大大減輕驗證工程師在晶元驗證時人為書寫大量測試的負擔，同時又可以減輕了人為因素在驗證過程中的影響，達到更好的測試效果。
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