gate array chip 中文意思是什麼
gate array chip
解釋
門陣列晶元-
This thesis primarily discussed the baseband processing of ss communication signal based field programmable gate array ( fpga ) asic chip
本論文主要討論和實現了基於fpga的擴頻通信信號的基帶處理。 -
After the investigation of the general technology of hardware implementation, how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail, and the author develops the cipher chip of kasumi algorithm, the kasumi cipher card based on 32 - bits pci bus, the wdm device driver that used in windows2000 / xp, and the software to demostrate encrypting data link. finally, an application demostration is constructed with all the above implementation
在此硬體實現的結果晶元基礎上，設計了32位的基於pci總線的kasumi加密卡，編寫了windows2000 xp下的windows驅動程序模型（ wdm ）驅動程序和鏈路加密應用程序，由此構成一個應用演示系統，作為研製結果的應用評估，為進一步進行第三代移動通信系統相關安全技術研究和開發提供了基礎條件。 -
In this paper, the method of digital evolvable hardware is studied based on the dynamical reconfiguration of field programmable gate array ( fpga ). in the paper, firstly, the basic conception and theory of ehw are roundly introduced and the structure characters of ehw chip are analyzed. secondly, the thought of standard evolutionary algorithm is discussed and the flow of improved evolutionary algorithms is analyzed
本文首先較全面地介紹了硬體演化技術的基本概念和原理，分析了演化硬體晶元的結構特點；其次，討論了標準演化演算法的思想並對改進型演化演算法的流程進行了分析；然後著重分析了演化硬體實現中的關鍵技術，對其實現方案進行了深入的研究，文中分別採用外部演化和內部演化兩種方式對不同的應用電路進行了演化。 -
The method of design of system on chip ( soc ) based on the field program gate array ( fpga ) is also introduced
並對課題中採用的基於現場可編程門陣列（ fpga ）的片上系統（ soc ）設計方法進行了介紹。 -
And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time
其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。 -
For the high - speed digital signal processing, the structure of fpga and dsp is widespreadly adopted. dsp is more featured in the implementation of complicated algorithm, while field programming gate array ( fpga ) shows more advantage in its flexibility of design, simplicity of system configuration, modification and maintenance. in the paper, the hardware system of the spaceborne radar is based on the structure of fpga and dsp, of which the signal processing part is accomplished with one fpga chip and multi dsps
Dsp適合完成結構復雜的演算法;現場可編程邏輯陣列（ fpga ）適合完成高效、演算法固定的任務;與專用集成電路（ asic ）相比， fpga優點主要在於其很強的靈活性、可在線配置、修改和維護方便等優點。本文工程中的星載雷達信號處理和控制系統就是採用dsp + fpga的方式。其中信號處理採用的是xilinx公司的virtex -和virtex系列fpga和多片analogdevices公司的tigersharcts101的硬體電路結構。 -
This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions
本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。 -
The design of cdma terminal chip is a very actual value and extensive application problem in the field of cdma technology application. with the development of micro - electronics technology, the design of integrated circuit has stepped into the age of soc ( system on chip ), which provide a brand - new method for cdma communication system project. in this paper, a design of cdma2000 1x spread modulation soc has be researched with large scale field programmle gate array device, and make a certain results
Cdma終端晶元設計是cdma技術應用領域中一個具有重要實際應用價值和廣闊應用前景的研究課題。隨著微電子技術的發展，集成電路設計進入了片上系統時代，這為cdma移動通信系統設計提供了一個全新的技術手段。本文將基於cdma技術，用大規模可編程邏輯器件對第三代移動通信cdma20001x的擴頻調製片上系統設計做了進一步的探討和研究，並取得了一定的成果。
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