gate delay 中文意思是什麼
gate delay
解釋
門信號延遲-
Also, in case of a breakdown or serious delay in tram service due to traffic accidents leading to unfinished trips, passengers can get off the tram quickly via the front gate without paying for the trip
此外，假如發生電車故障或交通意外等事故令服務嚴重受阻，以致電車未能把乘客送抵目的地，乘客即可不需繳付車資而迅速從前門下車。 -
A time measurement for a given computer word to pass a given point as in serial storage delay - lines. all of the bits of a word must pass through the input control gate ; the beat is then the sum of all the bits times
在串列存儲延遲線中，計算機字通過某指定點的一種時間度量。該字的所有位必須通過輸入控制門，拍則是所有位時間之和。 -
The tracking method of interference delay is studied and simulated. referring to late - early loop gate, a method that applies to this system is proposed. slight adjustment of delay difference is done by interpolation, so the whole digital structure is obtained
以數字通信中的遲-早門環路為基礎，提出了適用於pcma系統的跟蹤環路，並且利用插值的方法實現了時延差的微調，得到全數字化的設計結構。 -
The problem in high speed signal process, such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，穩定的時鐘信號是本課題的目標。高速信號處理所遇到的常見問題，如寄生參數，門電路延遲是設計難點。 -
The circuit is based on the conventional delay - superposition algorithm realized by the field programming gate array ( fpga ). the circuit makes it possible to deinterleave and track with pri in real time
本文還利用fpga對重頻跟蹤電路進行了設計，根據延遲重合法提出一種新的實現方案，由於不用進行首脈沖的確定，使得實時跟蹤成為可能。 -
When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。 -
An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束 -
Trigger gate delay
觸發門脈沖延遲 -
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform
由於製造設備本身存在微小誤差，具體門的延時並不相同，而是在一定范圍內變化，引起波形變化的時間不確定。 -
Delay gate generator
延遲選通脈沖發生器
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