gate density 中文意思是什麼
gate density
解釋
等效門電路密度-
A model of the interface state density distribution near by valence band is presented, and the dependence of the threshold voltage on temperature, the c - v characteristics and the subthreshold characteristics are predicted exactly with this model ; the effects of s / d series resistance on the output characteristics, transfer characteristics and effective mobility of sic pmosfets are analyzed. thirdly, the output characteristics and the drain breakdown characteristics are modeled with the procedure medici. the output characteristics in the room temperature and 300 ? are simulated, and the effects of gate voltage. contact resistance, interface state and other factors on sic pmos drain breakdown characteristics are analyzed
提出了一個價帶附近的界面態分佈模型，用該模型較好地描述了sicpmos器件閾值電壓隨溫度的變化關系、 c - v特性曲線以及亞閾特性曲線；分析了源漏寄生電阻對sicpmos器件輸出特性、轉移特性以及有效遷移率的影響；論文中用模擬軟體medici模擬了sicpmos器件的輸出特性和漏擊穿特性，分別模擬了室溫下和300時sicpmos器件的輸出特性，分析了柵電壓、接觸電阻、界面態以及其他因素對sicpmos擊穿特性的影響。 -
By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability
然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。 -
Abstract : a new approach, gate - capacitance - shift ( gcs ) approach, is described for compact modeling. this approach is piecewise for various physical effects and comprises the gate - bias - dependent nature of corrections in the nanoscale regime. additionally, an approximate - analytical solution to the quantum mechanical ( qm ) effects in polysilicon ( poly ) - gates is obtained based on the density gradient model. it is then combined with the gcs approach to develop a compact model for these effects. the model results tally well with numerical simulation. both the model results and simulation results indicate that the qm effects in poly - gates of nanoscale mosfets are non - negligible and have an opposite influence on the device characteristics as the poly - depletion ( pd ) effects do
文摘:提出了一種新的建立集約模型的方法，即柵電容修正法.此方法考慮了新型效應對柵電壓的依賴關系，且可以對各種效應相對獨立地建模並分別嵌入模型中.另外，利用該方法和密度梯度模型建立了一個多晶區內量子效應的集約模型.該模型與數值模擬結果吻合.模型結果和模擬結果均表明，多晶區內的量子效應不可忽略，且它對器件特性的影響與多晶耗盡效應相反 -
We can obtain the trap density by measuring the change of gate voltage of mos capacitance under constant current stress and the change of high frequency c - v curve before and after the stress
該方法根據電荷陷落的動態平衡方程，測量恆流應力下mos電容的柵電壓變化曲線和應力前後的高頻cn曲線變化求解陷階密度。 -
Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大 -
The analytical solutions to 1d schr ? dinger equation ( in depth direction ) in double - gate ( dg ) mosfets are derived to calculate electron density and threshold voltage
摘要推導了雙柵mosfet器件在深度方向上薛定諤方程的解析解以求得電子密度和閾電壓。 -
Namely, the electric field at the drain - side edge of the gate decreases with the increasing of negative charge density in the surface, so the breakdown voltage of gaas mesfet ' s will increase
表面受主態的增多使表面負電荷密度增大，表面聚集的負電荷可以分散漏側柵邊緣處的電力線密度，減弱了柵靠漏一側的電場強度，擊穿電壓提高。 -
Solving process of trap density and extracting of correlative parameters in thin gate dielectric
薄柵介質陷阱密度的求解和相關參數的提取 -
The results show that charge to breakdown qbd depends not only on the gate oxide quality but also on the voltage stress, current density and the gate oxide area
結果表明：相關擊穿電荷q _ （ bd ）除了與氧化層質量有關外，還與電壓應力和電流密度以及柵氧化層面積有關。
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