hardware cost 中文意思是什麼
hardware cost
解釋
硬體代價-
The top concern of development is how to read the image of bank paper and then recognize its code exactly. in consideration of cost and uers " convenience, single chip computer or dsp is used in the hardware design
研製這種設備的關鍵是掌握紙幣號碼圖像的讀入和識別技術，為了節約成本和使用方便，紙幣號碼讀入識別系統一般採用單片機或dsp來實現。 -
A last-minute cancellation on a rush order for military hardware cost us a staggering $ 1200.
有一張軍用器械的緊張定單在最後一分鐘取消了，使我們損失了1200美元。 -
The design based - on pci bus updates software and hardware handily, economizes cost
這種總線結構設計靈活性強，軟硬體升級方便，節約成本。 -
It is possible to reduce hardware cost by testing smaller-sized.
採用較小尺寸的試驗發動機可以減少零件的費用。 -
The total cost of the system's hardware could run to $150 million or more.
這套系統的設備總價值可達一億五千美元或更多。 -
Currently most of multinational companies and excellent domestic enterprises pay much attention to how to attract and retain talents, therefore focusing on this issue, i make a summary of some effective practical skills and cases on how to attract, take care and retain talents in it enterprises in the sector of hr management in it enterprises. hereinto, issues as the focal point of retaining core talent plan in it enterprises, how to analyze that who is the key talent in enterprise, what is the cost of losing key talent of the enterprise, the reason for staff in leave on software and hardware factor of the company, how to analyze what kind of employees is likely to leave and what kind of steps should be taken to retain the core talents
目前許多跨國公司和國內先進企業都在特別地關注如何吸引人才並留住人才的問題，因此作為本文的重點闡述部分，在it企業人力資源管理領域的論述中我總結了it企業吸引人才、關注人才、留住人才的一些非常有效的具體實戰方法和案列，其中特別討論了作為it企業核心人才保留計劃的重點，企業應如何分析企業誰是企業的核心人才，失去核心人才的代價到底是多少，造成員工流失的軟硬體原因，如何分析哪種員工最容易流失以及採用何種策略留住核心人才的問題。 -
When a firm decides to install a computer, the cost of the hardware may only be half the total cost.
當一個工廠決定裝配一臺計算機時，硬體成本只佔總成本的一半。 -
The present shortage of radio spectrum results in large part from the cost and performance limits of legacy hardware established during the past century
目前無線電頻譜壅塞的現象，大多起因於上個世紀製造的老式硬體設備在成本與效能上受到限制。 -
Abstract : the author stated the low cost retrofit using distributed control system to replace the existing control system of sulphuration equipment. the functional configuration of the distributed control system, the hardware and software of the system, and the communication between system and each layer of network are introduced in detail
文摘:提出採用集散型控制系統對現有的硫化設備控制系統進行低成本改造，詳細介紹硫化車間集散型控制系統的功能配置，系統的軟、硬體設計，系統及各層網路之間的通信。 -
The improved algorithm not only inherits the fast convergence trait from rls and realizable systolic array from qr _ rls, but also eliminates square - root operation and gets directly equalizer output signals from systolic array. so this algorithm has more simple operation, faster executing speed, less hardware resource and lower hardware cost. some different equalization algorithm are imitated on the qpsk communication system with multipath channel
其次對一些成熟的自適應均衡演算法（如lms演算法、 rls演算法、 qr _ rls演算法、逆qr _ rls演算法）進行了分析;介紹了一種改進后的無平方根的qr _ rls演算法，該演算法不但繼承了rls的快速收斂特性和qr _ rls演算法的systolic陣列可實現性，還取消了qr _ rls演算法的平方根運算，使演算法在硬體實現時運行速度更快，佔用資源也更少，同時該演算法還可由systolic陣列直接得到均衡后的輸出信號，運算量更小。 -
Viewing remote operating condition of distribution station automation system at any moment can not only save client soft hardware cost and but also avoid the maintenance of client and the repeat invest in development software
該系統具有通過瀏覽器隨時查看遠程配電所運行情況的特點，不但節約了客戶端的軟硬體費用，實現了免維護的客戶端，而且避免軟體開發的重復投資。 -
With the high development of the quantum circuits, the testability of the circuits will become a very serious problem. the method of testability design for rt circuits is proposed in the end of this paper, which has high testability and low hardware cost. only adding one extra mos transistor and two control ports, it can detect all open and short faults in rt circuits
隨著量子電路的飛速發展，由於其本身所特有的高集成度特點，電路的測試必然會成為越來越嚴重的問題，因此論文在最後就電路中常見的開路、短路故障提出了rt電路的可測試性設計方法，並針對具體的mobile電路進行了可測試性設計， pspice模擬結果表明達到了可測試的目的。 -
The core of the thermostat is pic16f873a mcu, with abundant on - chip peripheral equipment and the software. it has carried out some advanced function at least hardware cost such as the control parameter self - tuning, sensor identification and failure diagnosis, and is very easy to use
在硬體上，以微控制器為核心，利用pic16f873a集成了豐富的片上外設資源的特點，以最小硬體成本，配合系統軟體實現了pid控制參數自整定以及在線自動調整、傳感器類型識別及故障診斷等高級功能，十分方便用戶使用。 -
The media enhancement extension to mips - i compatible isa is physically realized in the processor core, and improves media processing performance effectively ( 2 - 4x ) with negligible additional hardware cost ( 2. 7 % ). a finite state machine ( fsm ) based centralized control scheme is presented in this paper to supervise the cpu pipeline activity
在系統晶元中媒體數字信號處理器核的設計中，在具體分析cpu流水線競爭和處理器異常的基礎上，本文提出並實現了一種基於有限狀態機的流水線運行控制方案，並從提高鐘頻和降低cpi值兩個方面優化處理器性能。 -
For the sake of lowering the hardware cost in the person - to - machine dialogue design, and saving the i / os in micro - controllers, we design a new display model using a new dynamic scanning display mode transmitting segment code and bit code alternately
摘要為了在人機對話設計中降低硬體成本，節約單片機的i / o口資源，通過串列動態掃描，即位碼和段碼交替發送的方式設計了一種新穎的顯示模塊，經調試，效果良好。 -
Considering the nonlinear difference of the gain and phase characteristic in solid state power amplifier ( sspa ), a parallel but imbalanced predistorting adjuster is used and the hardware cost can be reduced
考慮到固態功率放大器（ sspa ）幅度和相位非線性特性的差異，該系統採用幅度和相位不平衡調節的射頻預失真結構，降低了硬體成本。 -
When constructing the code, we pay much attention to hardware resource and concurrent executable ability of the verilog language to make the design close to the hardware working way, so we could get a high speed with a low hardware cost to satisfy the demand, performance and practicability
在代碼架構時，盡量貼近硬體的實現方式，充分考慮fpga晶元內部資源的合理開銷及verilog語言的可並發執行的設計理念，力求做到面積小而速度塊，以滿足產品成本、性能和實用性的要求。對于以後的soc （ systemonchip ）集成，具有一定的參考價值。 -
After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance
經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。 -
For the introduction of the virtual instrument technology, hardware cost is reduced, and development period is shortened, and expansibility of system is enhanced
虛擬儀器技術的引入，降低了系統的硬體費用、縮短了開發周期，增強了系統的擴展能力。 -
Combining integer with binary wavelet, a1video compression technique that only integer additions and shifts required is proposed in this paper, compared to the classic methods, the presented algorithm needs less hardware cost, and computational complexity is also reduced greatly
摘要將視頻壓縮和小波理論的最新發展整數小波和二進制小波相結合，提出只需整數加法和移位的視頻壓縮演算法，該演算法所需的硬體成本比一般的基於三維小波變換的演算法成本大大降低，而速度大幅度加快。
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