hardware description language 中文意思是什麼

hardware description language 解釋
硬體描述語言
  • hardware : 1 五金器具；金屬製品。2 （計算機的）硬體；（電子儀器的）零件，部件；（飛彈的）構件；機器；計算機...
  • description : n. 1. 記述，敘述，描寫；記載。2. 敘事文；（物品）說明書；相貌說明書。3. 種類。4. 作圖；繪制。
  • language : n 1 語言；（某民族，某國的）國語；語調，措詞。2 （談話者或作者所使用的）言語，語風，文風，文體。3...
  1. The off - the - shelf refinements are inspired by the operators of communicating sequential processes and map easily to programs in handel - c a hardware description language

    在過去的10年裡，人們進行了一些嘗試，試圖應用bmf方法從功能圖抽象描述中生成并行程序。
  2. The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly

    結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。
  3. After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder

    接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、鎖存以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍電路的電路板。
  4. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  5. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  6. Integrated circuit computer hardware description language verilog

    集成電路計算機硬體描述語言verilog
  7. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  8. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。
  9. ( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching

    （ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流
  10. Electronic design hardware description language vhdl

    電子設計硬體描述語言vhdl
  11. Behavioural languages - verilog hardware description language

    行為語言. verilog硬體描述語言
  12. Recurring to the technology of cpld / fpga, via the hardware description language, the equipment simulates some sspcs and the work - state of buses. besides, as a critical component in the system, owning to dsp ' s great task scheduling ability, dsp makes all the tasks work well. on the other hand, depending on the great communicational ability, a windows - based friendly intercommunicating interface is designed

    論文從本裝置的具體實現功能出發，採用自頂向下的設計思想，一方面使用硬體描述語言進行cpld fpga技術開發，完成多路sspc的多種工作狀態的模擬以及配電系統中匯流條的電能質量監測：另一方面利用dsp強大的任務調度能力，完成整個裝置各任務間的實時調度；此外dsp強大的通訊能力用來實現它與pc間的通訊，並設計了基於windows系統的友好的人機交互界面。
  13. Vhdl : very high speed integrated circuit hardware description language

    超高速集成電路硬體描述語言
  14. And the controller based on vhdl ( very high speed integration circuit hardware description language ) was designed under the fpga ( field programmable gates array ) integration environment with the values gained from the train of the neural network using matlab

    氣動柔性手指神經網路控制器是在已經對氣動柔性手指進行運動學和動力學分析的前提下，使用matlab對神經網路進行試訓，依據訓練所得的權值和閾值，在現場可編程門陣列集成環境下，基於超高速集成電路硬體描述語言完成的。
  15. Hardware description language

    硬體記述語言
  16. Hdl hardware description language

    硬體描述語言
  17. In order to make the speed of the function simulation faster, the system adopting vhdl ( very high - speed integrated circuit hardware description language ) to make simulation faster, at the same time this make it easy to transplant the circuit to other kinds of isp chips

    為了提高模擬的速度，對部分電路採用vhdl語言進行邏輯描述。通過實驗證明，在微波測距儀中採用在系統可編程邏輯器件，收到了很好的效果。
  18. This thesis consists of designing and implementing a jpeg encoder system that is compatiable with jpeg baseline mode using fpga ( field programmable gates array ) in standard hardware description language verilog

    本文探討了以fpga （ fieldprogrammablegatesarray ）為平臺，使用hdl （ hardwaredescriptionlanguage ）語言設計並實現符合jpeg靜態圖象壓縮演算法基本模式標準的圖象壓縮晶元。
  19. In this article, we study the implemetation of fpga for elliptic curve digital signature algorithm. based on number thesis 、 abstract algebra and complex thesis ， integrated information theory 、 cryptography and some specific relevant algorithm ， we ascertain the implementation of ecdsa for hardware project ： according to the design idea of hiberarchy and modularization, we adopt very high speed ic hardware description language ( vhdl ) as design input and simulate the design in every level and every model for the correct of the fundamental design. after finish the top design, we perform the whole simulation. then ， we carry out the timing simulation after the logic synthes and layout

    本文從實際應用出發，研究了橢圓曲線數字簽名演算法的fpga的實現：以基本的數論理論、抽象代數和復雜度理論為依據，結合信息論、密碼學的一些知識以及一些具體的相關演算法，確定了ecdsa的硬體實現方案：按照層次化、模塊化的設計思想，採用硬體描述語言vhdl作為設計輸入進行ecdsa的硬體設計；在每個設計層次和每個模塊都進行了模擬驗證，得以保證底層設計的正確性。在確保每個模塊的設計正確后，完成對電路的頂層設計，進行總體的模擬。
  20. First, the basic raster graphics algorithms for drawing 2d primitives are introduced, including edge coherence and the scan - line algorithm of triangle, brush algorithm of thick line ( and its improved method ) and midpoint circle and ellipse algorithm ; and the current situation of the advanced algorithms is also involved. second, the mapping of high level programming language to hardware description language is described, some principles of the conversion of algorithm to state machine are proposed also ; then, the implementation of basic graphics in hardware is discussed in detail, the state machines are drawn in the paper, and the interfaces of hardware are defined, block diagrams too, and the advanced algorithm of conic is proved ; finally, some issues about test are described, the results of simulation and synthesis are given in the last, and some detailed data are displayed in the appendix

    首先介紹了現有的基本圖形生成演算法，包括三角形邊相關掃描演算法，寬直線的線刷子演算法及其改進和圓形、橢圓的生成演算法，同時介紹了加速演算法的研究現狀；然後，討論了高級語言描述到硬體描述語言的映射，提出了演算法到狀態機抽象的規律；接著具體討論了基本圖形的硬體實現，給出了各演算法的狀態機圖，介面定義和實現框架，並且從理論角度給出了二次曲線加速演算法的證明：最後採用軟體工具進行測試驗證，給出了模擬、綜合實現的結果，並在附錄中有詳細的實驗結果數據。
分享友人
分享到 Line

分享到臉書