hardware trigger 中文意思是什麼
hardware trigger
解釋
硬體觸發-
In the paper, on the basis of research of static state and transient state in the scr and series connection valve circuit, the high voltage scr changing current valve device has been developed for ac - dc - ac high voltage commutatorless motor. the series connection valve circuit has been designed and simulated. the hardware design and software programming of trigger pulse system and monitoring system in the photo - electronic - photo fashion has been completed
無換向器電動機在火電廠等工礦企業的電機調速節能領域中有十分廣闊的應用前景，本文在對晶閘管元件和串聯閥電路的靜態特性和動態特性研究的基礎上，研製了用於交直交電流型高壓無換向器電動機的高壓晶閘管換流閥裝置，進行了串聯閥電路的設計和模擬，完成了電光電方式的觸發脈沖系統和監測系統硬體設計及軟體編程，並進行了裝置的實驗調試。 -
This dissertation majorly researchs and designs full digital dc driving system with fuzzy control. it makes a scheme argumentation firstly, analyzing the pid algorithm and fuzzy control algorithm the ordinary digital pulse trigger algorithm and the double remainder method of pulse trigger in detail, and fuzzy control and the double remainder method are put forward to settle the under - mentioned problems, namely, the new viewpoint and the task having finished in this dissertation as follows : ( 1 ) in rder to overcome the influence of dc motor ' s parameter changing with time and nonlinear on the control system performance, this dissertation adopts fuzzy control as outside regulator and pi control as inside regulator in double regulators of the full digital dc motor driving system design ;. ( 2 ) aiming at the pulse trigger reliability of the ordinary d igital pulse trigger being low and leaking the pulse or the order of pulse confusion, this paper adopts the double remainder algorithm with short response time high pulse trigger reliability good adaptability and anti - jamming ; ( 3 ) this dissertation adopts tms320lf2407 which has good performance as major control chip this chip has power function with fast calculation capability, and accomplishes the software and hardware design in the dc motor driving system with fuzzy control ; ( 4 ) this dissertation also puts emphases on anti - jamming in hardware and software ; ( 5 ) after having designed the sample of full digital dc motor driving system with fuzzy control, a lot of experiments are performed to verify the performance and settles problems during experiment. the result of experiment proves the feasibility of design
首先進行了方案論證，對模糊控制演算法和數字pid調節演算法、觸發脈沖的一般演算法和雙余演算法進行了詳細地研究分析，提出應用模糊控制和雙余法解決下述問題，即該論文主要的新見解和所完成的工作： （ 1 ）為了克服直流電機參數時變性和非線性因素對控制性能的影響，本設計中，雙閉環調速系統的外環採用模糊控制，內環採用pi控制，使系統在一定范圍內對直流電機參數變化和非線性因素影響有自適應能力； （ 2 ）針對常規數字觸發器演算法中觸發脈沖的可靠性不高，經常出現漏脈沖或是脈沖混亂的情況，本文採用雙余法，該演算法具有響應快，可靠性高，具有良好的適應性及抗干擾能力； （ 3 ）本設計中採用了速度快、功能強的tms320lf2407作為系統的主控晶元，應用該晶元完成系統的軟硬體設計： （ 4 ）本文對系統抗干擾的軟硬體措施進行了重點研究； （ 5 ）設計了具有模糊控制的全數字直流傳動系統原理樣機，並進行了試驗驗證，對試驗過程中出現的問題及時解決，最終實驗結果證明設計是可行的。 -
To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation
論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。 -
Based on the degree of urgency of going into graceful ospf restart, the reason of graceful ospf restart is divided into software - restart and hardware - restart, and the way of graceful ospf restart is divided into pre - restart mode and post - restart mode accordingly. after the compare with the traditional ospf realization method and the analysis on the mechanism of the trigger of graceful ospf restart and synchronization of link state database and the exchanging with the route management module ( rtm ), it is figured out that how to choose the restart mode and how to switch from pre - restart mode to post - restart mode, and how to synchronize the link state database, and how to define the interface and process flow exchanging with protocol supporting module, and how to deal with the forwarding table on the condition of multiple route protocols who also have the capability of graceful restart. finally, the idea of graceful ospf restart with two modes above was realized in the t series routers that belong to a telecommunication corporation
本文首先找出了引起溫和重啟的各種原因，然後根據溫和重啟的緊迫程度，提出把溫和重啟的原因分為硬重啟與軟重啟，並設計相應的前啟動模式與后啟動模式;結合傳統ospf協議的實現方法，通過對其觸發機制、數據庫同步機制、與支撐模塊的交互機制以及多協議同時重啟時路由同步機制的分析，解決了在溫和重啟過程中啟動模式如何選擇與切換、數據庫如何同步、與協議支撐介面如何定義與交互的問題，並揭示出在多協議同時進行溫和重啟過程中所必須遵循的一般規律，最終在一個通訊企業的t系列路由器上實現了兩種模式下基於ospf協議的溫和重啟。 -
Tdc using video trigger vecon - its vecon - its is a highly effective tool for modern traffic control and management without the need for hardware triggering devices
慧光路段交通訊息系統vecon - its是一個用於現代交通控制和管理的高效工具，而且不需要硬體觸發裝置，無需破壞道路。 -
The level 1 is a hardware trigger, which uses front - end electronic ( fee ) to do the real time event selection, in order to suppress the event rate to about 4 khz
即觸發判選系統（ triggersystem ）利用快速的電子學硬體進行實時的事例選擇，將事例率壓縮到4khz左右。第二級為在線事例選擇（ onlineeventfilter ） 。 -
Forcetrigger : it can let hardware auto generate a proper trigger when you can ' t get trigger in auto trigger mode
使硬體自動產生一個適當的觸發，當你在自動方式時不能得到觸發。 -
It includes the design of trigger circuit, high speed clock circuit, a / d digital and data acquisition circuit, time inter - plug circuit and pci interface circuit 。 3. the function debug of hardware and the result analysis
主要包括觸發電路的設計、高速時鐘電路設計、 a / d數字化與數據採集電路設計、時間內插電路設計和pci總線介面設計。 3 .硬體功能調試及其結果分析。
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