hardware verification 中文意思是什麼

hardware verification 解釋
硬體驗證
  • hardware : 1 五金器具；金屬製品。2 （計算機的）硬體；（電子儀器的）零件，部件；（飛彈的）構件；機器；計算機...
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  1. And it gave a detailed description of the downloading and verification on hardware. at last the fec system was applied in an audio transmission platform, which gave a good example for how to use the fec system

    最後介紹該前向糾錯電路在數字音頻無線傳輸中的實際應用，這為使用該糾錯電路提供了一個很好的實例。
  2. The work of this paper is coming from the project of electronic science & technology research institute, university of electronic science and technology of china ? soc software - hardware co - verification platform. this paper gives emphasis to the design and implementation of soc software - hardware co - verification platform monitor - control system. simultaneously, the interconnection tests of soc software - hardware co - verification platform, the fpga fabrics interconnection test and fpga with i / o slots interconnection test, are presented

    本論文主要圍繞soc軟硬體協同驗證平臺監控系統設計及其實現方法開展研究與討論，同時介紹了在對soc軟硬體協同驗證平臺進行測試過程中本文作者所做的「 fpga陣列互連線數量、連通性和數據速率測試」和「 fpga與i / o槽的互連線數量、連通性和數據速率測試」兩個測試項目方面的工作。
  3. This paper mainly focuses on the following three field : system structure, system hw / sw ( hardware / software ) partition. synthesis and verification. and presents a hw / sw co - design method based on ip ( intellectual property ) core. we use this method to design asip, and verify this virtual machine using instruction codes, ac - 3 codes and ts ( transport stream ) flow

    本文從晶元系統的整體入手，重點從系統的結構、軟硬體分割以及晶元系統的設計驗證三個方面對該晶元系統的設計做了深入的研究，提出了一種基於ip核的軟硬體協同設計方法，運用該方法對asip進行設計，並採用虛擬機的模型，採用指令集程序、 ac - 3解碼程序、 ts流程序進行模擬驗證。
  4. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  5. The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code

    系統設計是基於uart的實現演算法和設計指標要求，對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能，並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ，首先對系統的每個模塊進行功能和時序模擬，模擬通過之後，將整個系統的代碼在外部的輸入埠加上激勵，對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。
  6. A widely distributed software package that supports the formal verification of distributed systems - is an example of temporal logic model checking for hardware verification

    一種支持分散式系統的正式驗證且廣泛發布的軟體包是用於硬體驗證的時態邏輯模型檢查的示例。
  7. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  8. The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality. cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis. after hdl

    本文還設計了與軟體配合能讀、寫閃存的電路以及紅外遙控的硬體解碼電路，經hdl模擬及fpga驗證，所設計的兩種電路能完全滿足晶元商用要求。
  9. Your will set up a testing laboratory and maintain a verification environment for testing of application server products, which involves hardware and software installations, testing support

    懶得椅子一句翻譯這句了，總之就是：你要負責建立、測試、維護測試環境。
  10. This paper points that the activity of chip ' s verification is no longer hardware testing, but a hardware testing with basic rules of software testing

    在文中，通過對驗證活動的作用、驗證流程的分析，提出晶元的驗證已經不僅僅是硬體測試，而且是結合有軟體測試特點的硬體測試。
  11. Finally, the mechanical body of the mobile robot is designed specifically. the whole hardware framework is constructed. a reference platform is established for a further experimental verification of the algorithm

    最後，具體設計了差分驅動移動機器人的本體機構，並搭建了硬體的整體框架，為進一步的控制演算法的驗證提供了一個參考平臺。
  12. We verify the correctness of software in this co - verification platform, then use this correct software to verify the correctness of chip in the hardware verification platform

    Rtos通過修改硬體抽象層，把文件輸出重定向到新的顯示終端，就實現了異構平臺上的模擬。
  13. In the vector mode, all part of the design is implemented in the reconfigurable system ; stimulus and response vector is transferred serially to and from hardware. this mode improves the verification

    測試向量模式是將整個被驗證設計全部都下載到硬體平臺上，測試向量以數據流的形式在軟體環境和硬體平臺之間傳遞，對被驗證設計施加測試向量和接收響應。
  14. Co - emulation speed is also tested. in the co - emulation mode, a part of the design is simulated in the hardware simulator, the rest part of design are emulated in the reconfigurable system, two part of the design work cooperated to accelerate the verification speed

    聯合驗證模式將soc設計按照模塊進行劃分，將其中的一部分設計下載到硬體平臺中，而其餘設計駐留在硬體模擬器中，兩部分協同工作，利用硬體較計算機模擬器的速度的優勢，提高對被驗證系統的驗證速度。
  15. Because of lacking the hardware testing tools, a kind of low - cost testing scheme has been designed, and compared with other schemes. after adding usb host protocol stack to stite / os20 embedded operating system, and based on a large number of data verification and analysis, the conclusion was drawn that the usb host can communicate with usb devices correctly according to the protocol

    在缺乏硬體測試工具的情況下，本人設計了一種低成本的測試方案，並對這種方案進行分析比較，在大量數據驗證分析的基礎上得出結論:在stlite / os20嵌入式操作系統中加入本課題設計的usb主機協議棧后， usb主機能夠正確按照協議與usb設備進行通信。
  16. Simulation technology shall be utilized to simulate the real running of embedded hardware system to enable the software development and system integration implemented on a virtual stage, so as to complete the system model verification and running activity analysis before the manufacture of hardware prototype, avoiding the mutual wait between the software development and hardware development, in order to improve the development efficiency and lower the risks and costs

    利用模擬技術模擬嵌入式硬體系統的真實運行，使軟體開發和系統集成在虛擬平臺上進行，在硬體原型製造前就完成系統模型驗證和運行行為分析，避免軟硬體開發相互等待，提高開發效率，降低風險和成本。
  17. Recently, embedded software simulation development environment has been used widely, it shall be utilized to simulate the hardware system to enable the software development and system integration implemented on a virtual stage, so as to complete the system model verification and running activity analysis before the manufacture of hardware prototype

    利用軟體技術模擬嵌入式硬體系統的真實運行，在模擬平臺上進行嵌入式軟體的開發和系統集成。在硬體原型製造前就能夠完成系統模型驗證和運行行為分析，避免軟硬體開發相互等待，從而降低了成本，提高了開發效率和競爭力。
  18. Systems are verified in a transaction level not an event - based level which the existing verification methods are based on. this method has been successfully implemented through the soc hardware software co - verification system which is developed by me and other partners in our group. in the particular implement process, the whole system is divided into two parts

    在具體的實現過程中，將系統劃分為兩大部分來實現，軟體部分採用systemc這一高級的編程語言對軟體側進行建模，對數據結構進行抽象打包，實現數據的傳送、接收以及結果的查看等;在硬體部分，主要由veriloghdl語言編寫的狀態機實現bfm的功能，包括數據結構進行解包並信號級別信息的轉換， bfm與dut的數據通信，以及對信號進行打包傳送等工作。
  19. Md32 verification is implemented in both fpga hardware verification platform and software verification platform, which achieve unit, architecture and system verifications. md32 processor can be sufficiently verified on these platforms

    通過軟平臺中的單元驗證、結構驗證、系統驗證等步驟，以及基於fpga的硬平臺驗證，保證了md32處理器的正確性和完備性。
  20. This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions

    本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。
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