hdl hardware description language 中文意思是什麼

hdl hardware description language 解釋
硬體描述語言
  • hdl : 高密度脂蛋白
  • hardware : 1 五金器具;金屬製品。2 (計算機的)硬體;(電子儀器的)零件,部件;(飛彈的)構件;機器;計算機...
  • description : n. 1. 記述,敘述,描寫;記載。2. 敘事文;(物品)說明書;相貌說明書。3. 種類。4. 作圖;繪制。
  • language : n 1 語言;(某民族,某國的)國語;語調,措詞。2 (談話者或作者所使用的)言語,語風,文風,文體。3...
  1. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作: < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析,使其易用硬體實現; < 2 >基於可重構思想和特點,完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計; < 3 >採用自頂向下的設計方法,利用hdl語言對des / rsa設計進行功能描述,並完成軟體模擬,綜合和布線; < 4 >在可重構計算驗證平臺上進行演算法驗證,並對設計的可重構和設計的進一步優化進行討論。
  2. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析,並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分,建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分,採用asic設計中的高層次設計方法,使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述;利用多種eda工具對整個系統進行了模擬驗證與綜合。
  3. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga ( fieldprogrammablegatearray ) ,利用veriloghdl ( hardwaredescriptionlanguage )語言編寫了各個功能模塊,不僅使整個設計更加緊湊、穩定且可靠,而且可以根據實際的任務要求,在無需改變硬體電路板的情況下,通過修改硬體描述語言程序,即可修改電路功能。
  4. Hdl hardware description language

    硬體描述語言
  5. The hardware circuit boards are produced by a laser photoplotter according to the gerber files gererated from the schematic ( sch ) documents and the printed circuit board ( pcb ) documents. the cplds, programmed with the verilog hardware description language ( verilog hdl ), were completed after four steps : design, simulation, synthesis and fit. the software is developed with c language using direct i / o to communicate with the device through the isa bus computer interface

    其硬體電路由專業軟體設計出原理圖sch和印刷電路圖pcb生成,再gerber文件,然後光繪而成, cpld晶元編程(採用硬體描述語言veriloghdl )經過設計、模擬、裝配、下載完成,高級軟體編程採用c語言i / o方式利用isa總線介面與外設進行通信。
  6. The whole realization scheme of tpc decoding based on fpga, design flow and unit decoder are discussed in detail, of which sub - code is ( 64, 57 ) extended hamming code. the hardware description language and ide adopted are verilog hdl and quartusii - 5. 0

    文中以( 64 , 57 )擴展漢明碼為子碼,詳細闡述了tpc碼譯碼fpga實現的整體設計方案、實現流程和單元譯碼器的具體實現方法,在quartusii - 5 . 0環境下用veriloghdl語言實現了整個設計。
  7. With the help of newly developed advance electronics design automation ( eda ) technology, some roles and tens or hundreds of components of traditional instruments could be replaced or redesigned by means of large scale programmable logic chip ( cpld / fpga ) with the characters of the high integration, designed with hdl ( hardware description language ) and supporting iap ( in application programming ) and isp ( in system programming )

    而隨著eda技術的飛速發展,大規模可編程邏輯晶元cpld fpga應運而生。這類晶元可以替代幾十甚至上百塊通用ic晶元,而且,因其可用硬體描述語言進行晶元設計、支持在線編程和在系統編程等優點而備受青睞。
  8. The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel

    以fpga ( fieldprogrammablegatearray )為控制核心,採用串列a / d變換器和通道隔離技術,實現了8通道并行採集和測試數據分時存儲功能,利用veriloghdl ( hardwaredescriptionlanguage )設計vxi寄存器基介面電路及各通道的控制電路。
  9. Hdl : hardware description language

    硬體描述語言
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