hdl- 中文意思是什麼

hdl- 解釋

  • hdl : 高密度脂蛋白
  1. The bovine seminal plasma proteins bind to epidid - ymal spermatozoa via their interaction with choline phospholipids after ejaculation. in addition, they interact with bovine sperm capacitating factors, heparin and hdl

    射精后， bsp蛋白結合在精子表面磷脂酰膽堿位點，並與產道中獲能因子肝素、高密度脂蛋白（ hdl ）結合。
  2. One of the first series of controlled laboratory studies providing translational evidence for a molecular reason to maintain high levels of daily low - intensity and intermittent activity came from examinations of the cellular regulation of skeletal muscle lipoprotein lipase ( a protein important for controlling plasma triglyceride catabolism, hdl - c, and other metabolic risk factors )

    最初的一系列對照性實驗室研究提供了一些來自於骨骼肌脂蛋白脂肪酶翻譯水平的證據，從分子機制解釋了每日低強度和間歇性運動的細胞調節機制。
  3. High density lipoprotein cholesterin, hdl - c

    高密度脂蛋白膽固醇
  4. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  5. How hdl can protect the coronary circulation is not as yet firmly established.

    HDL究竟如何保護冠狀循環，迄今還沒有肯定的解答。
  6. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  7. Some scientists now think that each time you work out, the postexercise boost in hdl may help sweep your blood vessels clear of some of the artery ? clogging gunk

    一些科學家現在認為每次鍛煉后高濃度脂蛋白的增加可以使你血管中一些阻塞動脈的粘性物質得以清除。
  8. Bsp proteins can potentate sperm capacitation induced by heparin and hdl in vitro and bsp proteins can also stimulate cholesterol efflux from spermatozoa

    Bsp蛋白與精子的獲能及頂體反應有密切關系。
  9. Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard

    圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。
  10. Thi s dissertation first describes syntax, semanteme and method of modeling hardware of veri1og hdl and vhdl in detai1 so that strong abi1 ity of designing and simu1ating waveform is represented in hardware circuits

    本文首先對兩種硬體描述語言veriloghdl和vhdl在語義、語法及硬體建模方法進行了詳細的描述，說明它們在硬體電路波形表示方面有較強的設計與模擬能力。
  11. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  12. The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl

    在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。
  13. This paper systematically presents the whole design process of a cryptogrammic chip based on reconfigurable architecture. firstly it begins with a brief introduction to the background of the cryptogrammic chip design, and it clearly states the characteristic and the researching thoughts of cryptogrammic chip design with hdl. then the design environment and cipher algorithms are introduced briefly

    本文系統地論述了基於可重組體系結構的密碼晶元設計的全過程，文章首先闡述了該設計的課題背景，給出了使用hdl方法設計密碼晶元的特點和研究思路，然後對晶元的設計環境作了簡要說明，並對密碼演算法進行了簡單介紹。
  14. It is an important character that using hdl describes function and behavior of logic device or system hardware

    使用硬體設計語言來描述邏輯器件及系統硬體的功能和行為是硬體描述語言編程設計方法的一個重要特徵。
  15. 19 farzan fallah, pranav ashar, srinivas devadas. simulation vector generation from hdl descriptions for observability - enhanced statement coverage

    本文以可觀測性語句覆蓋評估準則為例，提出了計算可觀測性語句覆蓋率的方法。
  16. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  17. High level data link control hdl procedure

    高級數據鏈路控制規程
  18. Main characteristics include object - oriented language core, interfaces between vera core and hdl implemented by interface definition and port variables, complex concurrency control implemented by programming construction ( fork / join ) and data structures ( event, mailbox and semaphore, etc ). all these help vera successfully model hardware properties

    主要的特點是：面向對象的語言內核；通過界面定義和埠變量等實現了vera語言內核和硬體描述語言的介面；通過編程結構fork join和數據結構（事件、郵箱和旗語）來實現復雜的并行控制，實現對硬體特點的模擬。
  19. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  20. Optimal design for phase accumulater of dds based on verilog hdl

    相位累加器的一種優化設計
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