hierarchical memory 中文意思是什麼
hierarchical memory
解釋
存儲器層次結構- hierarchical : adj. 1. 僧侶統治（集團）的。2. 統治集團的。3. 等級（制度）的。adv. -cally
- memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
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In some cases a data part includes a structure, which is a hierarchical layout of structure items that each define an area of memory
有時數據部件包括結構條目的分層布局，在該布局中，每個部分定義一個工作區。 -
To provide a real - time relational and hierarchical view of a single set of data in memory. for more information, see
Dataset也可用於以xml形式編寫關系數據，並且可以與xmldatadocument同步，以提供內存中單個數據集的實時關系及分層視圖。 -
16 aggarwal a, alpern b, chandra a, snir m. a model for hierarchical memory. in proc. the 19th annual acm symp
并行計算模型包括共享存儲的第一代并行計算模型，分佈存儲的第二代并行計算模型，層次存儲的第三代并行計算模型等。 -
Liner table structure based on hierarchical storage is designed. it is used to store performance information in memory and log file
完成了分級存儲的線性表結構的設計，作為性能情報共享內存存儲結構和性能日誌文件存儲結構。 -
Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology
然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。 -
The hierarchical - based method is one of the clustering analysis methods to deal with big size data sets. with the limited resource, such as memory, cpu, and so on, it can get the best clustering result by use some algorithm structure
在聚類分析方法中，基於層次的方法是處理較大數據集中較為常用的方法之一，該類方法在有限的資源（如內存、 cpu ）下，通過採用一定的演算法結構，得到盡可能好的聚類結果。
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