instruction cache 中文意思是什麼

instruction cache 解釋
指令高速緩沖存儲器
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • cache : n. 1. （探險者等貯藏糧食、器材等的）暗窖，密藏處。2. 貯藏物。3. 【計算機】高速緩沖內存。vt. 1. 貯藏；密藏；窖藏。2. 【計算機】把…儲存到硬盤上。
  1. Itc instruction trace cache

    指令追蹤緩存
  2. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  3. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  4. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  5. This paper discusses msu ' s design, implementation and verification, implements the integration of the " longtengrl " system and studies the optimization of instruction cache

    本課題組設計的「龍騰r1 」微處理器晶元，指令系統與motorola公司的powerpc603e兼容，體系結構自主設計。
  6. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  7. This paper introduced a much more precise sampling method using cpu hardware performance counters ( chpc ) to provide cpu data like instruction cycles, cache misses, branch prediction, and so on, and given detail scene of software status

    摘要引入了基於cpu硬體性能計數器的性能數據採集和分析方法，從軟體運行時刻的細粒度參數入手分析軟體運行時刻的性能表現，從而更為準確地反映系統實際的動態運行狀態。
  8. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here

    該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。
  9. Instruction to force the cache line containing the modified instruction to storage

    指令，強制包含有修改過的指令的高速緩存行進行存儲。
  10. In order to gain more performance improvement 8k data cache and 8k instruction cache are used in ck510

    這些改進使c - core性能大大超過m - core 。整數運算能力是嵌入式cpu中重要的性能指標。
  11. In order to make better use of instruction fetch units, we also propose some new strategies, memcount policy and precount policy, base on cache miss rate and branch predict taken rate

    該演算法在多線索條件下， cache的缺失率相比單線索條件下的random演算法與lfu演算法而言有較為明顯的降低。
  12. 3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies. to improve cache performance under sma model, the paper introduces hardware software co - operative optimization

    3針對多線程模式下訪存負荷加重的問題，為sma模型設計了軟硬體協同預取機制，並為sma模型設計了cachefilter來消減無效預取。
  13. And in fact, the problem is exacerbated by the fact that a media app pushes data through the data cache much faster than a static app pushes code through the instruction cache

    事實上，這是由於動態媒體程序需要以遠遠高於靜態程序填充指令的速度來填充數據。
  14. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed

    指令讀取器產生讀取位址以供快取記憶體讀取快取區塊內的指令。
  15. In order to solve the problems about unfixed instruction length, stack - orientation and addressing virtualization in jvm instruction set, the instruction fetch unit, stack cache and mechanism of address translation in java chip system are studied

    為了解決java虛擬機指令系統中指令不定長、面向堆棧和地址虛擬化等問題，本文研究了java晶元中取指部件、堆棧緩沖部件和地址轉換機制以及相應物理存儲器的管理等關鍵技術。
  16. If there is no instruction cache, this subroutine may be a no - op

    如果在你的目標機上，沒有指令緩存，則可能不做任何操作。
  17. Instruction to invalidate the instruction cache line that will contain the modified instruction

    指令，使將要存放修改後指令的指令高速緩存行無效。
  18. On sparc and sparclite only, write this subroutine to flush the instruction cache, if any, on your target machine

    只在sparc和sparclite平臺上，這一功能調用用來刷新指令緩存。
  19. It is a risc microprocessor, has a six - stage pipeline, with separated data cache and instruction cache

    銀河ts - 1採用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。
  20. An instruction cache miss will occur when fetching this instruction, resulting in the fetching of the modified instruction from storage

    當取這個指令時會發生指令高速緩存失敗，結果就會從存儲器中取得修改後的指令。
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