instruction cycles 中文意思是什麼

instruction cycles 解釋
指令周期數
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • cycles : 石頭剪刀布
  1. Education, with its cycles of instruction so carefully worked out, punctuated by textbooks - - those purchasable wells of wisdom - what would civilization be like without its benefits

    教育，以其教學周期如此精心地安排，並以教科書- -那些可以買到的智慧源泉- -予以強化，如果不受其惠，文明將會是個什麼樣子呢？
  2. On succeeding instruction cycles, it will fetch instruction from locations 301, 302, 303, and so on

    在隨后的指令周期里，它將依次從301 、 302 、 303地址單元取指令，依此類推。
  3. This paper introduced a much more precise sampling method using cpu hardware performance counters ( chpc ) to provide cpu data like instruction cycles, cache misses, branch prediction, and so on, and given detail scene of software status

    摘要引入了基於cpu硬體性能計數器的性能數據採集和分析方法，從軟體運行時刻的細粒度參數入手分析軟體運行時刻的性能表現，從而更為準確地反映系統實際的動態運行狀態。
  4. There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost

    從消除信號阻塞到進程執行下一個指令之間，必然會有時鐘周期間隙，任何在此時間窗口發生的信號都會丟掉。
  5. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  6. Finally, by using hardware / software co - evaluation method to calculate the memory space the cpu cycles used and the gates that the extended instruction added, the performance of the whole system is analyzed

    最後，通過軟體上統計存儲空間和運行時間，硬體上對比添加指令硬體單元前後的綜合門數的軟硬體協同評估方法分析了添加指令后的系統性能。
  7. In this dissertation, the hardware / software co - design flow and ac3 decoding algorithm is analyzed and the ac3 audio decoding on the virgo risc - core. then the extended instruction is added to lessen the cpu cycles used and to reduce the memory space used by the decoding program

    其次，本文在分析軟硬體協同設計流程和ac3解碼演算法以及risc核virgo上實現ac3音頻解碼的基礎上，擴展指令集增加特殊指令減少了ac3解碼的時間和解碼程序佔用的空間。
  8. And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper

    為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間，又要達到單周期完成一條運算指令的吞吐量指標，本文提出對ex級進行可伸縮超流水擴展的思想，提出並實現了一種高性加比的切換控制方案。
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