instruction pipeline 中文意思是什麼
instruction pipeline
解釋
指令管線化- instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
- pipeline : 導管
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Research on instruction parallelism - based software pipeline
基於指令并行的軟體流水線研究 -
There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。 -
It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc
它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。 -
The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block
設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology
本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。 -
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too
詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。 -
The aim of mips pipeline is that one instruction completed in one period averagely
Mips流水線的設計目標是要達到平均每個時鐘周期完成一條指令，這就是流水線的極限速度。 -
Pipeline increase the cpu efficiency greatly, but the exist of instruction correlation make the pipeline block and delay frequently, as a result it can ’ t achieve the aim that one instruction completed in one period averagely
但由於流水線中指令相關等問題的存在，常常使流水線發生阻塞延遲，使得指令不能夠在預定的時刻完成，因而無法達到極限速度的目標，更無法超越該速度。 -
For increase the cpu efficiency more, base on the research of existing 32 - bit mips pipeline, this paper create the double - launching pipeline. by this design, one or more than one instruction completed in one period averagely, and increase the cpu efficiency remarkably
為了進一步提高流水線的執行效率，超越流水線的極限速度，本文在對現有32位mips流水線進行研究的基礎上，創新性地提出了基於32位mips架構的雙發射流水線設計方案。 -
Design of 3 - stage instruction pipeline 51 core
一種採用3級指令流水線的51內核設計 -
Reducing pipeline delay using two instruction fetching units
通過兩個取指令部件消除流水線控制相關延遲 -
The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique
該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。 -
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching
（ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流 -
Instruction to clear the instruction pipeline of any instruction that may have already been fetched from the cache line prior to the cache line being invalidated
指令，清除所有指令的指令管道，那些指令在高速緩存行被設為無效之前可能早已被取走了。 -
It is a risc microprocessor, has a six - stage pipeline, with separated data cache and instruction cache
銀河ts - 1採用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。 -
And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper
為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間，又要達到單周期完成一條運算指令的吞吐量指標，本文提出對ex級進行可伸縮超流水擴展的思想，提出並實現了一種高性加比的切換控制方案。 -
This processor processes 9 - stage pipeline, and risc instruction set. its operation frequency is capable of achieving over 150mhz
該數字信號處理器的cpu具有先進的vliw結構內核、九級流水線，具有類似risc的指令集，它的工作頻率可達到150mhz以上。 -
Isa is divided into three parts according to the design consideration of md32. rich addressing and operation modes are supported in md32 isa. risc / dsp pipeline partition rules are given based on the relations between instruction set and data path design
在md32設計中採用了具有自身特色的設計方法，探索出一套面向risc dsp指令結構的微結構設計原則和方法，如并行設計、內部流水設計、集中控制等。
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