instruction timing 中文意思是什麼

instruction timing 解釋
指令時序
  • instruction : n. 1. 教育,教導。2. 教訓,教誨。3. 〈 pl. 〉 指令,訓令,指示,細目。
  • timing : n. 1. 時間選擇。2. 定時,校時,計時,調速。3. 【自動化】同步;時限。
  1. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成,實現了任意窗口尋址等復雜指令操作,將整個處理器的數據通路與控制通路分離,減小了電路時延,從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求,構成了統一的、緊密聯系的、協調的md32系統結構。
  2. Following describing the system ' s organisation, we discuss the design and implementation of the system in detail including data paths, alu. to design the control paths, we start with the analysis of mcs51 instruction set, and then discuss the instruction execution procedure instruction and operation, and schedule of instruction timing

    Risc51ipcore控制通路的重點是兼容mcs51單片機指令系統的設計與實現,本論文從mcs51指令系統的分析入手,詳細討論了指令的執行流程、內部指令和操作的設置、指令的時序安排的設計與實現。
  3. The main work and achievements are as follows mcs - 51 microcontroller is studied. the result of the research is included mcs - 51 microcontroller work princip instruction system timing analysis feature picking up ; etc mcs - 51 microcontroller chip has been anatomized

    本論文的目的是設計mcs ? 51單片機晶元,主要工作和取得的成果如下:對mcs ? 51單片機進行分析研究,包括mcs ? 51單片機工作原理、指令系統、時序分析、特徵提取等。
  4. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼,以及多時鐘同步的控制流設計方法;進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
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