layout design 中文意思是什麼
layout design
解釋
布局設計-
The depot layout design for straddle type monorail system
跨座式單軌交通系統車輛段站場設計 -
In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical
在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。 -
Developing the lithography process models to properly characterize critical dimension ( cd ) variations caused by proximity effects and distortions introduced by patterning tool, reticule, resist exposure, development and etching, they are beneficial to develop a yield - driven layout design tool, the engineers could use it to automate the tasks of advanced mask design, verification and inspection in deep sub - micron semiconductor manufacturing
建立準確描述由於掩模製造工藝、光刻膠曝光、顯影、蝕刻所引起的光學鄰近效應和畸變所導致的關鍵尺寸變化的光刻工藝模型，有助於開發由成品率驅動的版圖設計工具，自動地實現深亞微米下半導體製造中先進的掩模設計、驗證和檢查等任務。 -
The infringements of integrate circuit layout design include illegal reproduction, illegally commercial use, etc. which are very dangerous to the society
布圖設計侵權行為主要表現為非法復制、非法商業利用等，社會危害性很大。 -
In the case of layout design, discussed the effect and application of the transistor matching in the circuits design deeply. demonstrated the circuit layout check by lvs design
在電路的版圖設計方面，較深入地討論了晶體管的匹配在電路版圖設計中的作用和應用，通過lvs對電路的版圖檢查進行了具體說明。 -
Based on the existing regulation integrated circuits layout - design in our country, and compared with the legislations in other countries and areas, the author makes use of fundamental theories in intellectual property rights, and ways of comparison to probe protection by law about rights of layout - design, in order to contribute to theory research and legislation on this type of intellectual property rights
為此，筆者根據我國《集成電路布圖設計保護條例》的規定，對比其他一些國家、地區的有關立法例，運用知識產權的基本理論，採取比較的方法，嘗試對集成電路布圖設計的法律保護問題進行探討，以期能夠對集成電路布圖設計保護的理論研究和立法完善有所裨益。 -
Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently
文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小 -
In licensing another person to exploit his layout - design, the interested parties shall conclude a contract in writing
許可他人使用其布圖設計的，當事人應當訂立書面合同。 -
Looking out from lake, the small mass buildings hidden in hill and tall buildings afar forms an energic and dynamic complex image, in layout design, the land not suitable for construction are remained natural afforestation, the relatively concentrated complex and the green land compensate each other
從湖面望向山林，隱約在山林之間的小體量建築與遠處的高層建築形成了豐富有機的建築群體形象，在建築疏密安排上，將不宜於建築的用地保留為自然綠化，使較集中的建築群體與綠地相互襯托。 -
Tailless flying wing aerodynamic configuration being optimal selection in ucav general layout design
大展弦比復合材料機翼結構建模與氣動彈性分析 -
And i finished the layout design, chip test of line driver and equalizer in 2. 5gbps baseband copper cable transceiver and equalizer in the 1. 5gbps sata transceiver respectively. the main improvements and innovations in this thesis are as follows : 1 、 to design an analog equalizer tuned on - chip for 2. 5gbps baseband copper cable transceiver ; 2 、 to present an adaptive equalizer for 1000base - cx transceiver ; 3 、 to present an auto - gain control amplifier used in the adaptive equalizer for the 1000base - cx transceiver ; 4 、 to present an adaptive continuous - time gm - c filter in very high frequency for the adaptive equalizer for the 1000base - cx transceiver
論文主要的改進和創新有： 1 、設計了適用於2 . 5gbps基帶銅纜收發器系統片上可調的模擬均衡器電路； 2 、提出了一種新的適用於千兆以太網基帶銅纜收發器系統的自適應均衡器結構； 3 、設計了甚高頻自動增益控制放大器； 4 、設計了一種適用於千兆以太網基帶銅纜接收器均衡的自適應甚高頻連續時間gm - c二階帶通濾波器。 -
Reproducing or putting into commercial exploitation of one ' s own independently created layout - design that is identical with the layout - design of another person
（三）對自己獨立創作的與他人相同的布圖設計進行復制或者將其投入商業利用的。 -
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。 -
Layout design and verification is the last step
最後進行版圖的設計和物理驗證。 -
The traits of progressive die for ic lead frame have been introduced with emphasis on the ironing stage in layout design and stripping micro - adjustment, safety setup of the structure
摘要紹了ic引線框架級進沖模的特點並著重講述了其排樣設計中的整形工位和模具結構中的卸料、微調和安全機構，可供精密級進沖模設計參考。 -
Due to the influences of the international legislative trend, china enacted the regulation for the protection of layout - design of integrated circuits in 2001. however, as the development of the intellectual property right law was comparatively late, it result in failure in the performance of law execution
至此，集成電路知識產權的法律保護成為一種趨勢。在國際趨勢影響下，我國於2001年制定了《集成電路布圖設計條例》 ，但總體上發展時間不長，執法效果不佳。 -
Bst - urd9100 9120 remote range reader is a type of intergration reader that is able to identify quickly and again - interference, it can read at least 8 meter range. its aspect adopts intergration layout design install conveniently and provide many communication port
Bst - urd9100 9120遠距離讀寫器是一款識別速度快和抗干擾能力強的一體化讀寫器，具有至少8米有效讀寫距離。 -
This subject belongs to three - dimensional layout problems with behavioral constraints theoretically and concerns the knowledge of spacecraft design, mechanical engineering, computer science, mathematics, mechanics and system engineering. so it can be ascribed as the frontier fundamental and applied research of cross - discipline subject with np complexity theoretically. in term of engineering practice, this subject has extensive applications, such as layout design of spacecraft module, engineering machinery, submarine and shipping, tank, under - water suspension engineering, platform of marine drilling well, bullet train, multiple spindle box of machine tool, robot
該課題在理論上，屬帶性能約束的三維布局問題，涉及航天器設計、機械工程、計算機、數學、力學和系統工程等學科，為交叉學科前沿課題的基礎理論和應用基礎研究，具有np難度；在實踐上，具有廣泛的工程應用背景，如航天器艙、工程機械、潛艇、船舶、坦克、水下懸浮工程、海上鉆井平臺、高速列車、組合機床多軸箱、機器人等的布局方案設計問題。 -
Vertical layout design code in petrochemical industry
石油化工廠區豎向布置設計規范 -
Standard logic cells, memory design and io layout design
標準邏輯單元，存儲電路設計及輸入輸出單元版圖設計。
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