ldmos 中文意思是什麼

ldmos 解釋
橫向雙擴散
  1. A thin epitaxial layer ( 10gm ) ldmos device used n - burry layer structure was proposed in the paper during the high - voltage device design, which is helpful to improve the drive circu it ? technology

    在高壓器件研究中，提出了一種外延層厚度為10 m採用n埋層結構薄外延高壓ldmos器件，對進一步改進驅動電路的工藝有著積極的意義。
  2. Considering the shortcoming of thick epitaxial layer technology, author proposed a thin epitaxial layer ldmos used n - burry layer. through optimizing the n - burry layer ? length and impurity dose will increase the device ? breakdown voltage

    針對目前厚外延工藝的缺點，提出的薄外延ldmos採用n埋層，通過優化n埋層長度、注入劑量可提高器件耐壓。
  3. In a word, for the merged power ldmoss, vbr = 400v. for the low side ldmos, vbr = 425v, ron = 0. 1. cm2, ton 30ns ， toff 140ns. r = 6, for i = 0. 35a, p 靜態 = 0. 74w

    把該功率器件集成在spic的內部，使spic的效率更高、性能更好、成本更低。
  4. During the high - voltage device design, the thick epitaxial layer ldmos which is compatible with current technology was researched. this device used piecewise vld and multiple region structure f reduce field layer. the using of the f reduce field layer effectively reduce the surface electric field of the device, shorten the length of its drift region, enlarge the choice of range of the ion implant dose of the p layer, and effectively restrain the disadvantageously affection on the breakdown voltage of the interface charge qss

    在高壓器件研究中對與現有工藝相兼容厚外延ldmos進行研究，該結構採用分段變摻雜多區p ~ -降場層，有效降低器件的表面電場，縮短器件的漂移區長度，增大p ~ -降場層注入劑量的選擇范圍，並有效地抑制界面電荷qss對器件耐壓的不利影響。
  5. A breakdown model of thin drift region ldmos with a step doping profile

    器件多晶硅柵量子效應的解析模型
  6. In the model of on - resistance, we have considered the lateral doping distribution in ldmos channel and vertical doping distribution in drift region. then we provide the explicit dependence between on - resistance and doping distribution parameter

    導通電阻模型考慮了ldmos的溝道橫向雜質分佈和漂移區雜質縱向分佈的結構特點，給出了導通電阻與雜質分佈參數的明確函數關系。
  7. An entirely new structure of high voltage soi ldmos with located charge trenches in vertical and a lateral trench with a shape of u was studied. with lots of analysis on this new compound structure, the breakdown voltage was raised 30 % and size was reduced to 60 % of the common soi ldmos

    這樣，該復合結構不僅可突破普通高壓soimosfet器件的耐壓極限，同時也可以使器件尺寸減少30 %以上；是與國際水平同步的一項重要研究，對soi器件及其功率集成電路的研發具有重要的意義。
  8. It is represented the optimization and implementation of step drift doping profiles soi ldmos

    Soi階梯摻雜漂移區ldmos的優化設計與制備實驗。
  9. In this thesis, the optimization of soi step drift doping profiles ldmos is addressed. the work of the author included the optimization of soi single - resurf ldmos and ; design and implementation of a step drift doping profiles soi ldmos

    圍繞soi階梯摻雜ldmos器件的優化問題，本文從器件結構和工藝材料方面出發，借鑒已有理論，進行了soisingle - resurfldmos的優化研究以及soi階梯摻雜漂移區ldmos的優化設計及器件制備實驗。
  10. We studied the resurf, trench - gate, 3d - resurf ldmos. we designed the power switch ic based on epitaxial simox substrate, satisfying the requirements of the user. this ic can sustain 60 ~ 80v shutdown voltage overshot

    在此基礎上，本文設計了性能滿足用戶要求的，基於esoi襯底結構的功率開關集成電路，該集成電路可承受60 ~ 80v的反向過沖電壓，並具有過流，過壓等保護電路。
  11. Lateral high - voltage power device ldmos has advantages of high - voltage, large gain, wide dynamic range, low distortion and compatibility with low - voltage circuit process

    橫向高壓功率器件ldmos有耐高壓、增益大、動態范圍寬、失真低和易於和低壓電路工藝兼容等特點。
  12. It ought to be compatible with low - voltage circuit process and satisfy requirement of high - voltage and large current this paper deeply discusses threshold voltage, on - resistance and current characteristic of ldmos, and builds the approximately accurate model of these electrical parameters

    本文討論的ldmos結構是pdp選址驅動晶元設計的一個關鍵問題，該結構實現了與低壓電路工藝的兼容，並滿足耐壓高、電流大的實際需要。
  13. The main work of the author includes the drive circuit design, research of high - voltage ldmos device which breakdown voltage is 1000 - 1200v, the drive circuit ? technology design and layout design, technology experiments of device and circuit

    主要工作包括：驅動電路的電路設計；耐壓為1000 1200v的高壓ldmos器件研究；驅動電路的高低壓兼容工藝設計和器件與電路的版圖設計；高壓器件與驅動電路的工藝實驗。
  14. For the reason of the same frequency, we use the ldmos fet. there are three development for the middle power amplifier : the first stage power amplifier, the drive stage power amplifier and the last stage power amplifier

    本文針對遙測遙控放大器與其頻率相同的特點，對中功率放大器進行研究。本文對固態線性功率放大器的研製包括：前級放大器的研製、驅動級放大器的研製、末級放大器的研製。
  15. The model of threshold voltage solves the problems of nonuniformly doped channel, short channel effect, implantation for adjusting threshold voltage, edge capacitance of gate, etc. not only the model can be used in ldmos, but it can perfectly describe the short channel effect of threshold voltage for all other mos devices

    其中，閾值電壓模型解決了溝道非均勻摻雜、短溝道效應，調閾值注入，柵邊緣電容等問題。該模型不僅適用於ldmos ，也可以很好地描述所有的mos器件閾值電壓的短溝道效應，嚴格證明了短溝道效應會引起閾值電壓的減小。
  16. 4 ). analysed the relationship of sensor ’ s voltage and ldmos ’ voltage, which will benefit from the intergration of high voltage device and low voltage circuit. 5 )

    4 ）分析一種帶sensor端ldmos的檢測端電壓與功率管電壓的關系，以期更好的設計高低壓集成的智能功率ic 。
  17. The design of the circuit ? key parameters including pulse width in the level shifter part and delay time of the filter circuit, and the necessity to add a limiting current resistor at source the ldmos were emphatic analyzed. author finished the design of each sub - circuit

    對電路關鍵參數高低壓電平位移脈沖寬度、高端濾波電路濾波寬度的設計及在ldmos源端加入限流電阻的必要性進行了重點分析，完成了各單元電路的設計。
  18. The research of ldmos current characteristic involves the linear current region, cut - off saturation region, quasi - saturation region and providing the simplified analytical expressio n

    Ldmos電流特性的研究涉及了器件電流線性區、夾斷飽和區和準飽和區，並給出了簡化的電流特性解析表達式。
  19. The two structure ldmos was compared by simulation with medici software. the result is that their breakdown voltage is almost the same and the thin epitaxial layer ldmos ? ron is lower

    通過medici模擬對兩種器件進行比較，結果為兩種器件耐壓相當，薄外延ldmos導通電阻略低。
  20. So the research on spic is moving on steadily. second, the history of ldmos is presented, and several kinds of ldmos is displayed and discussed. then opt - vld, which was invented by pro

    第三章介紹spic的三種常見隔離技術和本次工作中的創新型隔離技術，並給出了模擬結果進行分析。
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