line decoder 中文意思是什麼
line decoder
解釋
行譯碼器-
Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in
電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器 -
The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier
Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。 -
Detail specification for electronic components. semiconductor integrated circuit ct54ls138 ct74ls138 3 - to - 8 line decoder
電子元器件詳細規范.半導體集成電路ct54ls138 ct74ls138型3線? 8線譯碼器 -
Bcd detail specification for electronic component. semiconductor integrated circuit - cc4028 cmos 4 - line to 10 - line decoder with bcd - in
電子元器件詳細規范.半導體集成電路cc4028型cmos 4線? 10線譯碼器 -
Detail specification for electronic components. semiconductor integrated circuit ct5442 ct7442 4 - line - to - 10 - line decoder bcd - to - decimal
電子元器件詳細規范.半導體集成電路ct5442 ct7442型4線- 10線譯碼器bcd輸入 -
Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology
然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
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