logic channel 中文意思是什麼
logic channel
解釋
邏輯通道-
The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.
通道計數器和解碼器向數據鎖存和傳送邏輯電路提供通道選擇信息。 -
By using the yearly data of water - sand that is gotten by a couple of adjacent hydrologic station in yellow river lower reaches, this paper makes use of kinds of math methods looking for the nonlinear disturbance among all of the factors, and introduces the thinking of analysis, logic, conclusion, inference, and random to nonlinear hydrologic forecasting. it realizes the valid approximation of the water level process in erodible - bed channel
本文選擇黃河下游兩對相鄰水文站多年水沙資料，藉助多種數學方法尋找其中的非線性擾動項，將隨機數學中分析、邏輯、歸納、演繹、隨機的思考問題方式引入到非線性水文預報中，實現沖淤河道相應水位過程的有效擬合。 -
Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo
本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。 -
The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit
該系統硬體包括數字信號處理器晶元、前向輸入通道、液晶顯示器、模擬量輸出部分、鍵盤輸入部分、保護電路部分和邏輯控制部分。 -
In the process of implementation, it is essential to find a scheme to solve the following problems : ( identification of the logic channel type of signals from handsets, which is the key to determine which decoding module should be called
本論文的主要任務是用dsp ，通過幾個模塊之間的聯調，實現基帶處理的接收模塊的功能。接收模塊主要完成gmsk解調和解碼功能，並將所解碼出的手機上行的信號傳遞給信令模塊。 -
A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up
設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。 -
According these points, configuration and arithmetic is presented, and result which is simulated in computer is contented. dual - cpu system ( tms320c3x and aml86 ) is selected as fareware environment of simulation, in which high - speed logic calculation of dsp ( tms320c3x ) and controlling capacity of aml86 is utilized well. design of hf channel simulation is realized in the fareware system
在硬體設計上，我們選用了雙cpu （ tms320c3x和am186 ）系統作為我們的模擬硬體平臺，充分利用了dsp的高速運算功能和am186的協調控制功能，在此平臺上實現了高頻通道模擬器的設計。 -
The output drivers are designed to drive external n - channel power mosfet and igbt. the internal logic assures a dead time typically being 1. 25 s to avoid cross conduction of the power devices
為保證圖騰柱輸出的功率器件安全工作不產生穿刺（ crossconduction ） ，內置典型值為1 . 25 s的死區時間。 -
A combinational logic element having at least one input channel
一種至少有一個輸入通道的組合邏輯元件。 -
However. with the shift of economy and society, it must be transformed, too. on case of guangxi universities, it has come out many problems : 1, single subject of fiance and vest system ; 2 power exceeded ; 3, university run society ; 4 produce lower efficiently ; 5 people attached to the unit. the original cause is that our party ' s comprehension of " soviet moedel " about the highe r education modernization. traditional culture stockpile, higher education institution during the revolution period and effect of planned economy. by historical logic. theory research and current studyjt ' s transform is inevitable and urgent. what ' s more. guangxi has satisfied the require - ments, such as law, economy, social culture surroundings for the contract system of higher edu - cation. lt includes five ideas : l the system of varied channel finance and invest universities in " outer - system " ; 2 modern macro - managementin " outer - universty " ; 3 specialized of higher education ; 4 contract cooperating between univerties whom clear property rights ; 5, contract management to univerty itself
無論從歷史邏輯、理論分析還是現實考察，從單位制到契約制的高教制度變遷都有其必然性和緊迫性。在具備了良好的法律、經濟、社會文化外部環境后，可進行廣西高教契約制的建造。其主要內容有： 1 、在「體制外」實現多渠道高教財政投資體制和多元化辦學體制； 2 、在高校外部，政府權限有了設定，實行現代高教宏觀行政管理體制； 3 、高校自身的專業化特色設定； 4 、高校間明晰產權的契約合作； 5 、高校內部契約管理體制。 -
The process and system utilize fuzzy logic in determining whether or not to " admit, " i. e., allocate a virtual channel ( vc ) for, new communications ( or calls ) to the node
這個程序及系統應用模糊邏輯來決定是否要"充許" （也就是決定是否要分配一個虛擬通道） ，新的通訊連結（或呼叫）進入這節點中。 -
The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation
在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
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