master processor 中文意思是什麼
master processor
解釋
枝理機-
By combining the system developing levels with the application environment, the redundancy level was positioned in the model - level redundancy, a / d connected in series with the master as the redundant unit, the bi - processor models drive on outer model
結合系統開發層次與使用環境，將冗餘級別定位於模塊級冗餘，提出了以a d與主機串聯形成的處理器模塊為冗餘單位、雙處理器模塊共同驅動一套外設的模型。 -
On account of actual demand, an ip core of 32bits / 33mhz pci interface module based on fpga has been designed by virtue of vhdl, and the 32 bits microblaze processor soft core has been embedded into this fpga. so, a fast and highly efficient pci master / slave interface, a local processor and other control logic are integrated on one chip of fpga
根據實際需求，利用vhdl硬體描述語言設計了基於fpga的32位/ 33mhz的pci介面模塊的ip核，並內嵌xilinx公司的32位軟處理器核microblaze ，從而在一片fpga上就實現了快速高效的pci主從介面和本地端處理器及其他控制邏輯。 -
The features of pci local bus, signal definition, command definition, bus operation and the addendum of the pci local bus specification, revision2. 3 are introduced briefly at first. then the structure and function of plx pci 9656 pci bus mastering i / o accelerator are summarized including : pci 9656 ' s three data transfer modes ( direct master, direct slave, and dma ) and direct connection to three processor local bus types ( m mode, c mode. j mode )
在簡要介紹了pci總線的特點、 pci總線的信號、命令和操作規范、 pci總線的配置空間以及有關最新pci總線規范pci2 . 3里的一些新增和修改的內容之後，本文概述了plx公司的pci總線專用控制器pci9656結構和功能，並介紹了pci9656的發起者、從設備、 dma三種工作模式以及m 、 c 、 j三種局部總線介面方式。
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