memory signal 中文意思是什麼
memory signal
解釋
記憶信號-
An integrated maximum value memory and a signal inverse function can be turned on and off at any time by a keyswitch
最大值記憶功能和信號反轉功能可以隨時通過按鍵開關來開啟或關閉。 -
The development of single chips and analyzers at home and that of overseas compared, a kind of pocketable dual - channel and multi - function signal analyzer, based on dsp, are researched with the functions of dynamic analyzer, data logging acquisitor, start - up / coast - down analyzer and dynamic balancer, etc. and the functions data acquisition, storage, display and analysis of vibration signal are validated in practice, high - speed float point data calculation ability, large memory space and simple operation are the characteristics
高性能單片機尤其是dsp功能晶元的採用及用戶技術要求的不斷提高，使得信號分析儀的功能越來越完善，在比較了國內外單片機和信號分析儀的發展現狀后，開發研製了一種基於浮點dsp晶元tms320c32的便攜式雙通道多功能信號分析儀，兼有動態信號分析儀、巡檢數采器、起停車分析儀、動平衡儀等多種儀器的功能。 -
Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard
圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。 -
According to signal processing capcity and the memory of sharc21060 chip, six shrac chips are used in practically processing. every chip takes on different task, and it basically realized streamy parallel processing
根據信號處理運算量的需求以及sharc21060晶元的內存量，在實際處理中，共使用了6片sharc晶元，各晶元承擔不同的任務，基本實現了流水線式的并行處理。 -
Based on the dsp development board, the author finishes the hardware debug about the multi - channel buffered serial port ( mcbsp ) receiving the output signal from the gps if collector and resolves the software program of the receiving buffer of the multi - channel synchronous serial data, data integration, udp datagram encapsulation and network interface driver, etc. the real - time udp datagram receiving, data frame de - encapsulation and high speed data memory are implemented, and a friend application interface with windows message is developed on the pc
基於dsp開發板，作者完成了dsp的多通道緩沖串口（ mcbsp ）接收gps中頻接收機輸出信號的硬體調試，並解決了多通道同步串口數據的接收緩沖、數據合併、 udp數據報裝幀及網路介面驅動等軟體編程。在pc端，通過mfc的網路應用開發類casyncsocket實現udp報的實時接收、數據解幀譯碼、高速存貯，利用windows消息機制開發了應用程序友好界面。 -
The voice recording instrument adopts 8bit pcm and 4bit adpcm voice coding and decoding mode, can record the eight - channel voice signal simultaneously. it can save the recorded data in the flash memory or in the pc through the ethernet. the recorded voice signal data also can be played back
該語音記錄儀採用8位pcm或4位adpcm語音編解碼方式工作，可實現8路音頻輸入信號同時錄音;能夠將錄制的數字語音數據存儲在nand型flash中或通過以太網介面上傳到pc機存儲;能夠將錄制的數字語音數據進行回放。 -
The fourth chapter : in this chapter, it introduces the hardware designing of the dsp system based on pci bus and states every module of the hardware designing : circuit of signal adjusting, filter circuit of anti - overlap, circuit of data - acquisition automatically, expanding circuit of dsp memory, circuit of voltage matching, interfaces circuit of pci etc. it also includes theoretic basis and procedure of pcb designing
第四章介紹基於pci總線的dsp系統硬體設計。敘述了硬體設計的各個模塊：信號調理電路、抗混疊濾波電路、自動數據採集電路、 dsp存儲器擴展電路、電平匹配電路、 pci介面電路等，以及pcb設計的理論基礎和設計過程，並給出了設計和調試的結果。 -
2 rayleigy and weibull distribution ground clutter for airborne phased array radar ( apar ) general pulse signal was simulate with method of zero memory nonlinear transform
二、利用零記憶非線性變換法實現機載相控陣雷達常規脈沖情況下的瑞利分佈、韋伯爾分佈的地面雜波模擬。 -
Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory
摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。 -
Agilent 54621d, 54622d, 54641d, and 54642d mixed - signal oscilloscopes msos provide the channel count, memory depth,
證和查錯中，也有許多工程師主要依靠雙通道或四通道示波器， -
With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。 -
The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )
本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。 -
The product has the following characters : all - purpose input, completed separated signal channels, collection of the signal data by scanning, the display technique of lcd big screen, flash memory ; capacious compatible floppy disk, 36 types of signals, multiple alarms, communication of rs232 / 485 and hart confered - link with a view to second generation technique of the field - bus. during the developing course, i used the method of reliability design to design hardware, and researched carefully the process of weak signal. pass to practice, the product has achieved all aim of the design
系統在功能上實現了萬能輸入，信號通道之間的完全隔離，信號的掃描採集，大屏幕lcd顯示技術， flash存儲器進行數據存儲，大容量的具有兼容性的電子軟盤， 36種信號方式，多種報警方式， rs232 / 485通訊，以及著眼于下一代的現場總線技術的hart協議介面等。 -
So this thesis mainly discussed how to get micro - leaking - signal from pipeline and how to transmit these signal from collecting place to base - station with wireless way, or, how to store and transfer these signal from memory to computer
本文重點研究了如何提取和分析壓力管道的泄漏信號，以及對提取系統的軟硬體實現和泄漏信號分析法的提出。硬體有無線採集和有線存儲兩套小型化數據採集系統。 -
This system ' s hardware adopts dsp - embedded controller, which can process digital signal independently. the controller communicates with pc by accessing memory. on the side of controller, c language is used to write the interpolation program and the interruption service program, while on the side of pc, visual c + + is used to write programs in which functions of editing nc - code, real - time control and human - machine interaction interface is fulfilled
該數控系統的硬體採用了具有獨立數字信號處理功能的dsp型運動控制器，控制器通過內存訪問與pc機通信，使用c語言編寫了控制器端的中斷服務和插補程序，使用visualc + +編寫了pc端的數控代碼編輯、實時控制和人機交互界面程序。 -
( 3 ) research of brain ' s memory structure according to needs of brain stimulation, author provides an idea to build memory structure, which could be the static state of brain, by using a three layers structure of signal, conception and knowledge
（ 3 ）人腦記憶結構模型及形態構成知識的產生針對人腦模擬的要求，提出了構建記憶結構的思路，方法和總體框架。 -
The system is able to complete the data sample of 32 signals input, and has the ability to sample simultaneously of per 4 signal inputs. the conversion is 8 bits, and the sample rate of per channel is not less than 400hz. in addition, this data conversion system also have the ability of data storage without power supply, and the data size in flash memory is amount to sample 5s " of 32 signal inputs
整個採集系統完成對32路輸入信號的采樣，而且可對每4信號路進行同步采樣， ad轉換精度為8位，每路信號采樣率不低於400hz ，另外系統還具備斷電數據保存功能，採用flash存儲器保存5秒的采樣數據，同時也具備與計算饑的epp并行通信介面。 -
There are several advanced functions in control system of fed driving based on fpga. the special al875 can support multi - display format from qvga 、 vga 、 svga to xga in the digital rgb graphics and video frequency. using vga interface and d / a conversion technology, it can monitor data signal and control signal real time. the control of buffer storage carry out seamless link by double frame memory refurbish. osd can control menu and text to adjust state by double display
完成的基於fpga的新型fed驅動控制系統具有幾種先進的功能:採用專用於rgb圖形/視頻信號數字化的al875晶元，可以支持從qvga 、 vga 、 svga到xga的多種解析度的顯示格式;採用vga介面技術和d / a轉換技術，用於實時監控整個系統中的圖像數據信號和控制信號;採用乒乓刷新控制機制對緩存進行控制，實現數據讀寫操作的無縫連接;採用osd在屏顯示單元，實現控制菜單、文本在屏幕上的疊加顯示。 -
The best way to avoid the need to allocate memory in a handler is to allocate, in advance, space for signal handlers to use
避免在處理器分配內存的最好方法是，為信號處理器預先分配要使用的內存。 -
Research of effect of crack width on the magnetic memory signal
裂縫寬度對磁記憶信號的影響的研究
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