memory-core system 中文意思是什麼
memory-core system
解釋
記憶核心系統-
This design is the first solid - state memory system for satellite, which can confront with multi - clock sources and multi - data sources compatibly. it is the fist design that integrates all functions of data processing and control into a single programed logic device. this design can be an ip core that can bring large advantage when system upgrade in the future
本星載固存系統是我國星載固存系統中第一個採用多數據源，多時鐘源進行兼容設計的單一固存系統；第一個採用ip化、參數化設計思想，採用單一邏輯編程器件做為固存系統唯一控制部件，為以後系統升級帶來了很大好處；第一個採用功耗均衡思想來降低系統功耗。 -
After analyzing and summarizing the characteristics of technology sentence, translation memory is selected as the core of technology translation system in the paper, some key technologies, including word segmentation, similarity computation, alignment, english sentence construction and the design of bilingual dictionary, example corpus, sub - trunk gallery, are deeply studied
論文在分析和總結工藝語句特點的基礎上，提出用翻譯記憶技術作為工藝翻譯系統核心，並分別對分詞演算法、相似度計算、對齊方法、譯文生成等關鍵技術進行了研究，建立了雙語詞典庫、例句庫和子塊庫。 -
In order to reach the requirement of applying for the multi - objective and multi - parameter measuring, we adopt the distributing computer controlling system which the at89c52 single chip was used as core in the system, also the circuit of signal conditioning and data acquisition and processing are all integrated in the system. we use nixie tube to fullfill the displaying function and adopt high - capacity memory to record the data of production process
同時為適應工廠要求對多目標、多參數進行監測的要求，採用了分散式計算機控制系統，該系統以at89c52單片機為核心，內部集成了信號調理、數據採集與處理、顯示等電路並擴展了大容量存儲器以保存最近幾次生產過程的檢測數據，同時還採用了rs485網路總線技術可以方便的將數據傳輸給上位控制中心。 -
For the teaching the hardware pwm inverter is designed, including the choice of power module, filter tache, auxiliary power supply, brake unit and protection circuits. in addition data sampling system is contrived with encoder and current / voltage sensors. the control circuit with tms320f240 for the core is presented at last. the circuit includes memory extension, d / a converter digital i / o interface and the interface of the serial port. the way of space vector pwm realization is briefly introduced in this paper
接著，設計了pwm電壓型逆變器，其中包括主迴路功率模塊與濾波環節、控制電源、制動單元及保護電路設計。另外還利用霍爾元件與編碼器設計出數據採集系統。最後，給出了基於tms320f240的最小系統，包括存儲器擴展、串口擴展、數字i o介面以及空間矢量pwm的實現。 -
In the last part, some core test bench of dsp applications are implemented on the dpc with our multi - level memory system and on the c64 platform respectively
本文給出了設置scratch - padsram之後的數據分配方法，並測試證實了scratch - padsram對性能的提高影響明顯。 -
The task of realtime display on lcd and the complicated control arithmetic are implemented in this smps system, and a microcontroller with high resolution, high speed, high integration, large memory is necessary. in this paper, the design theory of s / h ware module which forms the smps control module and the design scheme is discussed in detail. in this system, the digital compute - control module is implemented with samsung ’ s high resolution, high integration, arm core microcontroller s3c44b0 and ad converter with 16bit resolution produced by ad company, ad7705. the ad7705 implements the data acquisition of the voltage and current feedback signal, and transfer the data to microcontroller through spi bus, which is implemented with s3c44b0 ’ s gpio, for computation and display
本開關電源系統不僅完成lcd的實時顯示，還要完成復雜控制演算法，需要高速度、高精度、高集成度、大存儲空間的微控制器的支持。本文詳細的論述了構成電源控制模塊的各個軟硬體模塊的設計原理和設計方案。本系統提出了以samsung公司的高速度、高集成度的基於arm架構的微控制器s3c44b0與ad公司具有16位解析度的模數轉換器ad7705晶元構成數字採集運算控制模塊。 -
This paper projects a utility subdividing drive system of step motor, which consists of digital control module, drive module and power module, it uses at89c52 single chip processor as the core, it realizes the external event or generates control signal by i / o interface, timer and external interruption, the system introduce pld device and isp technology to the design of phase sequencer, it simplified circuit and improved the anti - disturbing capability by using abel - hdl language, this system can realizes data memory, velocity digital control and led display, etc. this paper adopted firstly the single - chip technique to design control system, which replaced old complicated logic control circuit and simplified test process
本文研究了一種實用的步進電機細分驅動系統，由數字控制模塊、驅動模塊和電源模塊組成，系統以at89c52單片機為核心，通過單片機的i o口、定時器計數器中斷來實現外部事件監控以及控制信號的產生，系統將可編程邏輯器件（ pld ）器件和在系統編程（ isp ）新技術引入到細分驅動環行分配器的設計，通過abel _ hdl語言編程實現硬體軟化設計和邏輯重構，大大簡化了電路，並提高了電路抗干擾能力。使系統實現參數存儲，速度數字控制，數碼顯示，進退刀控制等功能。 -
The analog circuit of the system in this thesis is composed with pre - positive circuit of 4 - probe electrode sensor and temperature - measure circuit. the digital circuit regards at89c55 single - chip as core, expanding ad, key in, display out and memory peripheral chips
系統硬體的模擬電路部分設計了四電極傳感器前置模擬電路以及熱敏電阻測溫電路;數字電路部分以at89c55單片機為核心，擴展了a / d ，鍵盤輸入，顯示輸出等基本功能。 -
The linux kernel and other core os components - including libraries, device drivers, file systems, networking, ipc, and memory management - operated consistently and completed all the expected durations of runs with zero critical system failures
Linux內核和其他核心os組件包括庫、設備驅動程序、文件系統、網路、 ipc和內存管理運轉穩定並完成了所有期望的運行期間，沒有任何嚴重的系統故障。 -
The core of epics is a distributed run - time database system that located in the memory regularly and stored run - time datum that is obtained from devices
Epics的核心是一個常駐內存的分散式實時數據庫系統，存放往來于設備間的實時數據。 -
In this solution, the embedded soft cpu ip core is used as the kernel digital module with its periphery controllers based on residual les. in addition, analog channel circuit is added to form an integrated dso system. this dissertation focuses on framework construction, gui design, memory management, message fifo management, other hardware drivers and describes design and implementation of software simulation system written in advanced languages
在這種方案中，使用了在fpga中嵌入cpu軟核作為控制核心，並用fpga晶元中剩餘的其他可編程邏輯資源構成該嵌入式系統的外圍器件，形成數字示波表的數字核心模塊，並配以模擬通道部分電路，組成了一個完整的數字示波表。
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