nmos 中文意思是什麼

Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。

An analytical mosfet threshold voltage shift model due to radiation in the low - dose range has been developed for circuit simulations. experimental data in the literature shows that the model predictions are in good agreement. it is simple in functional form and hence computationally efficient. it can be used as a basic circuit simulation tool for analysing mosfet exposed to a nuclear environment up to about 1mrad. in accordance with common believe, radiation induced absolute change of threshold voltage was found to be larger in irradiated pmos devices. however, if the radiation sensitivity is defined in the way we did it, the results indicated nmos rather than pmos devices are more sensitive, especially at low doses. this is important from the standpoint of their possible application in dosimetry

該模型物理意義明確，參數提取方便，適合於低輻照總劑量條件下的mos器件與電路的模擬。並進一步討論了mosfet的輻照敏感性。結果表明，盡管pmos較之nmos因輻照引起的閾值電壓漂移的絕對量更大，但從mosfet閾值電壓漂移量的擺幅這一角度來看，在低劑量輻照條件下nmos較之pmos顯得對輻照更為敏感。

Secondly, the radiation effects of the system of silicon gate si / sio2 ( silicon gate nmos and pmos ) implanted bf2 are made a deep systematic study. especially, the relationship between threshold voltage shift ( vth and vit vot ) in radiated mos transistor and irradiation dose rate, irradiation dose, irradiation temperature, bias voltage, device structure as well as annealing condition is explored emphatically

在此基礎上，對bf _ 2 ~ +注入硅柵si sio _ 2系統低劑量率輻照效應進行了深入系統的研究，著重研究了bf _ 2 ~ -注入mos管閾值電壓漂移（ vth和vit 、 vot ）與輻照劑量率、輻照總劑量、輻照溫度、偏置電場、器件結構以及退火條件的依賴關系。

Especially in cmos n - well integrated circuits technology, the body effect will cause the nmos threshold voltage following the pumping voltage to be lifted and then the highest pumping voltage will be limited

特別是在n阱集成電路工藝，體效應使得每一階nmos管的閾值電壓都不斷抬升，以至於電荷泵的最高輸出電壓受到限制。

The thesis has done the widespread investigation and study to the domestic and foreign ’ s technologies of analogy low voltage and low power, and analyzes the principles of work, merts and shortcomings of these technologies, based on the absorption of these technologies, it designs a 1. 5v low power rail - to - rail cmos operational amplifier. when designing input stage, in order to enable the input common mode voltage range to achieve rail - to - rail, it does not use the traditional differential input pair, but use the nmos tube and the pmos tube parallel supplementary differential input pair to the structure, and uses the proportional current mirror technology to realize the constant transconductance of input stage. in the middle gain stage design, the current mirror load does not use the traditional standard cascode structure, but uses the low voltage, wide - swing casecode structure which is suitable to work in low voltage. when designing output stage, in order to enhance the efficiency, it uses the push - pull common source stage amplifier as the output stage, the output voltage swing basically reached rail - to - rail. the thesis changes the design of the traditional normal source based on the operational amplifier, uses the differential amplifier with current mirror load to design a normal current source. the normal current source provides the stable bias current and the bias voltage to the operational amplifier, so the stability of operational amplifier is guaranteed. the thesis uses the miller compensate technology with a adjusting zero resistance to compensate the operational amplifier

本論文對國內外的模擬低電壓低功耗技術做了廣泛的調查研究，分析了這些技術的工作原理和優缺點，在吸收這些技術成果基礎上設計了一個1 . 5v低功耗軌至軌cmos運算放大器。在設計輸入級時，為了使輸入共模電壓范圍達到軌至軌，不是採用傳統的差動輸入結構，而是採用了nmos管和pmos管並聯的互補差動輸入對結構，並採用成比例的電流鏡技術實現了輸入級跨導的恆定;在中間增益級設計中，電流鏡負載並不是採用傳統的標準共源共柵結構，而是採用了適合在低壓工作的低壓寬擺幅共源共柵結構;在輸出級設計時，為了提高效率，採用了推挽共源級放大器作為輸出級，輸出電壓擺幅基本上達到了軌至軌;本論文改變傳統基準源基於運放的設計，採用了帶電流鏡負載的差分放大器設計了一個基準電流源，給運放提供穩定的偏置電流和偏置電壓，保證了運放的穩定性;並採用了帶調零電阻的密勒補償技術對運放進行頻率補償。

In order to get strain from the channel, by process, deposit si3n4 at nmos and adopt the silicon - germanium epitaxy on source / drain by pmos, can effective improve nmos and pmos electronic characteristic

中文摘要近年來，為了提升金氧半場效電晶體工作頻率及性能，尺寸不斷微縮，讓相同面積晶片可以擁有更多的電晶體數量。

In the third chapter, a methodologies to realize second - order band - pass filter with which center frequency tuned in a wide range using mcdi ( multiple output current - mode differential integrator ), these two kinds of mcdi are composed of pmos and nmos input transistors respectively, lastly we compare these two integrators " merits and disadvantages

第三章：提出了輸入級分別為pmos管、 nmos管的多輸出端電流模式全差分積分器，並由此構成了中心頻率連續可調的二階帶通濾波器，同時比較了二者的優缺點。

The proposed modulator uses 0. 35um standard cmos process, the nmos and pmos threshold voltage is 0. 54 volt and - 0. 48 volt, respectively, and the power supply is 1. 5 volt. the nyquist converter rate is 50 khz, oversampling ratio is 80. the proposed modulator can obtain 98db dynamic range, 16 bits converter resolution, and fits for high - fidelity, digital - audio application

本設計採用0 . 35微米標準cmos工藝，其中nmos和pmos晶體管的閾值電壓分別為0 . 54伏和- 0 . 48伏，電源電壓為1 . 5伏，奈奎斯特轉換率為50khz ，過采樣率為80 ，該調制器可實現動態范圍98db ， 16位的轉換精度，適合高保真數字音頻應用。

After structure design aimed to high transconductance, parameters of device structure are modified in detail. the simulation results of soi nmos with strained si channel show great enhancements in drain current, effective mobility ( 74 % ) and transconductance ( 50 % ) beyond conventional bulk si soi nmosfet. the strained - soi nmosfet fabrication process is proposed with lt - si ( low temperature - si ) technology for relaxed sige layer and simox technology for buried oxide

其次，根據器件參量對閾值電壓和輸出特性的影響，以提高器件的跨導和電流驅動能力為目的設計了strained - soimosfet器件結構，詳細分析柵極類型和柵氧化層厚度、應變硅層厚度、 ge組分、埋氧層深度和厚度以及摻雜濃度的取值，對器件進行優化設計。

Researched the methods to test interconect resource ( ir ) witch include interconnect lines and nmos switchs

研究完成了對互連資源（ configrableinterconnectresource ）的測試。

Semiconductor integrated circuits. detail specification of type jm2148h nmos 1024 4 bit static random access memory

半導體集成電路. jm2148h型nmos 1024 4位靜態隨機存取存儲器詳細規范

This is due to the fact that each transistor in a cmos circuit is actually made from a pmos transistor and an nmos transistor

這是由於cmos里的每一個晶體管都是由一個pmos和一個nmos晶體管組成的。

The use of edgeless nmos transistors in place of 2 - edgeless transistors eliminates the excessive radiation - induced edge leakage in many cmos parts after irradiation

為了測試最新設計的1萬門cmos門陣列的抗輻射水平，本文設計了一個cmos集成電路測試樣片。

Besides, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress by nmos and strain due to uniaxial compressive stress by pmos

但微影技術已經接近瓶頸，所以我們必須另外尋找能夠提升電晶體效能的方法，應變矽就是目前提升電晶體性能最熱門的方法。