parallel adder 中文意思是什麼
parallel adder
解釋
并行加法器-
The algorithm and its implementation of the leading zero anticipation are very vital for the performance of a high - speed floating - point adder in today s state of art microprocessor design. unfortunately, in predicting " shift amount " by a conventional lza design, the result could be off by one position. this paper presents a novel parallel error detection algorithm for a general - case lza
目前國際上已有很多演算法對前導0預測演算法進行了研究，但是出於設計方法和延遲等方面的限制，大部分前導0預測演算法都為非精確演算法，其預測結果可能與真實加法結果中前導0的個數產生一位的誤差，這個誤差需要在浮點加法的后規格化過程中進行修正，因此反過來又增加了浮點加減演算法的關鍵路徑延遲。 -
Design and implementation of a 64bit cmos parallel adder with modified architecture
并行加法器設計與實現
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