parallel processor 中文意思是什麼
parallel processor
解釋
并行處理機-
9 dakai zhu, melhem r, childers b r. scheduling with dynamic voltage speed adjustment using slack reclamation in multi - processor real - time systems. ieee trans. parallel distributed systems, 2003, 14 : 686 - 700
動態電壓調節是體系結構層的低功耗技術，由於系統運行的能量消耗與運行電壓成平方關系，在運行期間動態改變系統電壓可以極大的降低系統的功耗。 -
In this paper, real time torpedo homing system. which is based on adsp ? 2106x to be discussed. high speed signal parallel processor system is researched, it is made up of intel 80c186eb processor main board and adsp _ 2106x. it can be come true using this system for the accuracy parameter estimation of underwater target which moves on high velocity
本課題是以高速并行數字信號處理晶元adsp ? 2106x為核心，以intel80c186eb微處理器構成的cpu模塊為主控板，構成完整的高速并行數字信號處理機硬體系統，該硬體系統可以成功地實現現代魚雷自導的水下高速運動目標參量實時精估演算法。 -
Investigation and analyzing has been made by the science and the industry for architecture of the network processor and network applications to testify the high benefits that could be brought by good combination of the logic of network application and the parallel infrastructure of the network processor, which confirms that the logical parallelization in network applications and the paralleled hardware structure of network processor are the promising basics for potential excavating of network hardware and developing of high quality network applications
學術界和工業界致力於對網路處理器架構和網路應用程序二者各自的特性進行研究和分析，用以說明網路應用程序本身的邏輯特性和網路處理器的并行架構相得益彰。通過研究可以看出，網路應用程序本身的多個特性使其具有天然的可并行邏輯，這為充分挖掘其并行性和開發基於網路處理器的高質量高性能的應用程序奠定了基礎。再者，網路處理器專有的硬體架構為應用程序的并行執行提供了硬體基礎。 -
It has high efficiency advantage while network processor transfers packet editing commands between the packet editor and packet editing command generator, because it is a new parallel command transferring mode but net a serial mode
這種機制使得在網路處理器的包編輯器和包編輯命令發生器之間傳遞包編輯命令的效率得到了大幅度的提高。 -
This thesis mainly focuses on the multi - level parallelism development and performance optimization of scientific programs on this architecture, and our works are summarized as follows. ( 1 ) we put forward the multi - level parallel computing time model, which is suitable for smp cluster to analyze program performance from the micro - aspect. we also provide a multi - level parallel optimization speedup model based on the single - processor speedup factor, which can evaluate program performance from three parallel levels and guide us to improve the programs
本文圍繞這種多級并行體系結構中的超節點級、節點級和單機指令級三個層次的并行性開發與優化，在科學計算程序的綜合優化技術研究方面做了以下的工作與創新: （ 1 ）針對smp集群體系結構提出了多級并行計算時間模型，用於程序性能的微觀分析;將單機處理速度與加速比統一起來，提出了基於單機優化加速因子的多級并行優化加速比評價模型，該模型分別從三個并行層次的角度出發對程序性能進行評價，並指導對程序的改進與優化。 -
Then the vibration equations in the wheel / rail system dynamics are constituted again and the rigidity matrix, the damping matrix and the load matrix can be formed by different computer processor for the sake of increasing parallel computation efficiency
隨后在公式級對輪軌系統動力學振動方程組的組建進行了優化，將組建剛度矩陣、阻尼矩陣和荷載列陣模塊化。 -
Changing operations on the fly ? converting, say, a calculation of a matrix of numbers to a parallel - processing computation ? requires the relatively slow rewiring of connections between large blocks of transistors, not the individual elements ( gates ) that perform a processor ' s logic operations
若要以動態的方式改變操作（例如將數字矩陣的計算轉換為平行計算） ，得將大區塊電晶體間的連結緩慢地重新接線，而非直接改變處理器里執行邏輯運算的個別元件（邏輯閘） 。 -
After analyzing the characteristic of the parallel processing system, some problems about design missile - carrying processing system are pointed out ; network in the parallel processing system has become bottleneck and affect the performance of system, so the processing efficiency is analyzed in a multiprocessor system based on cluster - bus and some rules in designing the network in the multiprocessor system are brought out ; genetic algorithm is used for scheduling in the multiprocessor system, and a scheduling algorithm is described to suit arbitrary number of tasks, unequal task processing time, arbitrary precedence relation among tasks and arbitrary number of parallel processor, so that the schedule length will be minimized ; finally, an atr algorithm is mapped to a ring multiprocessor system, and a block diagram using dsp device is constructed. in chapter 4, the study is performed on real - time system hardware realization of atr. tms320c80 is selected as the kernel processor in multiprocessor system
為此，對一種由常用的dsp晶元組成的多處理器系統的處理器利用率進行了分析，提出了多處理器系統互連網路設計的基本原則；本章使用遺傳演算法作為實現多處理器調度的工具，提出了一種新的任務調度演算法，該演算法主要是為了解決在任務數任意、任務計算時間不相等、任務前趨關系任意、以及任務間存在通信和考慮任務存貯器要求的情況下，如何優化任務在各個處理器上的分配和執行順序，使得多處理器系統總的執行時間最小；最後對一個目標識別演算法進行了硬體實現優化分析，根據分析結果，將演算法映射到由dsp晶元組成的環形網路連接的處理器拓撲結構上，得到了多處理器系統的原理框圖。 -
The receiver unit mainly consisted of the digital down converter, matched filter, integration and dump module, power detector, symbol tracking processor, differential demodulator, parallel - to - serial conversion module, output processor and afc module
接收部分主要有數字下變頻、數字匹配濾波器、積分清洗、功率檢測、符號跟蹤處理、差分解調、並串處理、自動頻率跟蹤處理等模塊。 -
Technique. suppose there are six steps as in ieee arithmetic hardware in a floating - point addition as shown in figure 2. a vector processor does these six steps in parallel - if the i
向量處理器可以并行處理這六個步驟如果第i個數組元素是在第4個步驟中被添加的，那麼向量處理器就會為第（ i + 1 ）個元素執行第3個步驟，為第（ i + 2 ）個元素執行第2個步驟，依此類推。 -
Content addressable parallel processor
內涵可尋址并行處理機 -
Processor allocation strategies for parallel xml database systems
數據庫系統處理機分配策略 -
Finally, a new performance model of multi - dsp system architecture and task allocation and schedule is presented in virtue of distributed finite state machine ( dfsm ) and vhdl environment. chapter 1 gives a comprehensive description about the significance of research and the current research status of real - time dsp, parallel processing, fpga co - processor and vxi virtual instrument technology
第?章緒論部分闡述了選題的意義，介紹了高性能信息處理領域內實時信號處理技術、并行處理技術、 fpga技術和vxi總線技術的研究與發展現狀，並介紹了課題提出的背景與主要研究內容與任務。 -
So, we must design multimedia application - oriented computer architecture to fit the data processing demand of video compressing programs, we analyzed the parallelism of two representative video compressing programs - opendivx and tml9, and drew a conclusion that it is effective to run video compressing application programs on the processor which uses parallel arithmetic units
相對于視頻壓縮應用而言，普通計算機的處理能力大大落後于處理需求。因此，對于多媒體應用，必須採用并行的方法來解決，但是不能簡單地使用普通并行機，必須針對這部分應用的特點，採用并行的思想來設計面向多媒體應用的計算機體系結構。 -
Parallel computers have developed from the big special vector computer to the parallel mutiple processor, and now to the more popular cluster of workstation
并行計算機從以前的大型專用向量機，發展到并行多處理器系統，以及現在比較流行的工作站機群系統。 -
In software development, distribution, priority, task flow chart design, parallel schedule of tasks are discussed in detail. finally, elmc model is finished and tested with power system processor ( psp ), solid state power controller ( sspc ), and servo system
文中詳細分析了任務劃分、任務優先級分配、各任務流程圖設計及任務間的并行工作方式等；設計完成了elmc原理樣機，並與供電處理機、固態功率控制器和伺服控制系統進行聯合調試。 -
On the basis of summarization of the simulating technology of sonar signal, the paper brings forward the mathematics models of radiate noises of ships and torpedo, and simulates in computer ; tests the correctness of some pivotal methods through the simulation, on the basis of which, system scheme being brought out ; a parallel processor with twelve sharcs, combining with parallel processing theory and topographic configuration, is used to realize the algorithm of noise simulation on the basis of research on optimum distribution of algorithm and method of embedment in real time ; at last, gui, realized with vc + + language, is used to set parameters and control the whole parallel system flexibly and conveniently
本文在綜述聲納信號模擬技術的基礎上，首先提出艦船和魚雷輻射噪聲的模擬數學模型，並進行了計算機模擬實現；通過計算機模擬驗證了一些關鍵技術的正確性，並由此提出系統實時實現方案；構造了一個12個處理器的并行處理機? sharc陣列，結合併行處理理論和sharc陣列的拓撲結構研究了有關模擬演算法的最優分配及其嵌入整個聲納系統的方法，實時實現了噪聲模擬演算法。最後，使用vc + +語言編寫人機界面，靈活、方便地進行參數設置以及對整個并行處理系統進行控制。 -
This design can provide a high - speed path to a set of sharc parallel array processor. between this parallel processor and an analog signal acquisition module, the designed system can realize real time transmission
本設計的目的在於為一套sharc并行處理陣列機提供高速的數據通道，使其能與模擬信號採集模塊進行實時的數據傳輸。 -
Edge is one of the important characteristics of image, and it also is the element of several research areas, like computer vision and pattern identification. cellular neural network ( cnn ) is a parallel processor
邊緣是圖像中重要的特徵之一，是計算機視覺、模式識別等研究領域的重要基礎。細胞神經網路（ cnn ）是一種并行處理器，在圖像處理上有很大的發展空間。 -
Finally discusses several class different multi - dsp extended architecture based on vvp platform. chapter 3 analyzes the significance of dynamic reconfiguration of multi - dsp parallel processing system, introduce run - time reconfiguration technique of fpga. with comparison of the common used dynamic communication network in parallel processor system, proposes the new dynamic reconfigurable multi - dsp system architecture based on run - time reconfigurable fpga
第三章分析了多dsp并行系統體系結構動態可重構的意義，介紹了fpga動態配置技術，比較了現有的一些多處理器動態互連的設計實現方法，在此基礎上，提出了利用局部動態重構fpga技術設計實現實時動態可重構多sharc功能系統的新方法。
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