parallel-parallel logic 中文意思是什麼
parallel-parallel logic
解釋
並并行邏輯-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
Expert system has many merits. it has the ability of heuristic illation, and can explain for illation and append new knowledge in the knowledge database. but it also has obvious shortcomings, such as, poor ablitity in ka ( knowledge achieve ), inefficient and incomprehensive. the artificial neural network has the ablitity of parallel processing, associative memory, distributed storage of knowledge and high robust etc. it also has perfect characteristics of self - organizing, self - adaptive, self - learning. it specializes in visualize ideation but is short of logic ideation
專家系統在故障診斷領域得到廣泛的應用，專家系統具有許多優點，能利用專家的知識進行啟發式推理，能夠解釋其推理過程，並能夠不斷地、靈活地增加新的知識。但專家系統也存在明顯的缺陷：獲取知識能力差、效率低、范圍窄。可以說專家系統長于邏輯思維缺乏形象思維。 -
Through the simulation of large - scale circuit simulation proved that use the crossover tearing technology could detailed network structure, simplify the diagnostic process, and the neural network can parallel deal with the diagnosis information, and the logic operation can judge the information of the multi - fault. the illustrative simulation shows that it can increase the diagnosis speed and decrease the workload before test
通過對大規模模擬電路的模擬證明，使用交叉撕裂明細網路結構，簡化診斷過程，且運用神經網路組對信息進行并行處理，邏輯分析運算對多故障信息進行處理判斷，大大提高了故障診斷速度，減小了測前工作量。 -
In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework
另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。 -
In this paper, we developed a self - assembly model for dna - based parallel addition. the central feature of this model is to apply the parallel logic. we make the complexity analysis of the algorithm used here
這里，提出了一種利用dna進行兩個數的相加的模型，這一模型的思想是對兩數逐位并行相加，極大地利用了dna計算并行的特點。 -
For its characteristic of parallel logic and dispersed state, ca can be realized easily in hardware
元胞自動機的并行邏輯特性以及離散狀態等特性，使其易於硬體實現。 -
Modeling and simulation of fuzzy logic control strategy on parallel hybrid electrical vehicle
並聯混合動力汽車模糊邏輯控制策略的建模和模擬 -
When those ptvs are sequentially loaded to cut ( circuit under test ) from intelligent fault diagnosis system, homologous prvs ( parallel response vector ) are taken back. through test response analysis by expert system, intelligent fault diagnosis system can detect all fixed ' 1 ' logic fault, fixed ' 0 ' logic fault, and detect the majority of multi - line short circuit fault
當這些ptvs從pc機中依次加載到被測電路板后，相應的prvs （并行響應向量集）可以獲取供診斷系統進行測試響應分析，從而檢測出固定邏輯故障和橋接故障。 -
Then, a linear - time partitioning algorithm based on a linear ordering of nodes in a circuit for parallel logic simulation is presented
然後，提出一種在對電路中節點進行線性排序的基礎上的線性時間劃分演算法。 -
Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder
採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。 -
The programmable logic device is programmed and simulated vvith max + plus ii of altera corporation, and the program is down loaded to the device through byteblaster parallel port dovvnload cable
可編程邏輯器件由altera公司的max + plus編程並模擬，由所製作的並口傳輸電纜線下載到硬體。 -
Investigation and analyzing has been made by the science and the industry for architecture of the network processor and network applications to testify the high benefits that could be brought by good combination of the logic of network application and the parallel infrastructure of the network processor, which confirms that the logical parallelization in network applications and the paralleled hardware structure of network processor are the promising basics for potential excavating of network hardware and developing of high quality network applications
學術界和工業界致力於對網路處理器架構和網路應用程序二者各自的特性進行研究和分析，用以說明網路應用程序本身的邏輯特性和網路處理器的并行架構相得益彰。通過研究可以看出，網路應用程序本身的多個特性使其具有天然的可并行邏輯，這為充分挖掘其并行性和開發基於網路處理器的高質量高性能的應用程序奠定了基礎。再者，網路處理器專有的硬體架構為應用程序的并行執行提供了硬體基礎。 -
Peripheral devices in embedded systems are often connected to the mcu as memory - mapped i / o devices, using the microcontroller ' s parallel address and data bus. this results in lots of wiring on the pcb ' s to route the address and data lines, not to mention a number of address decoders and glue logic to connect everything
由於并行總線擴展時連線過多，外圍器件工作方式各異，外圍器件與數據存儲器混合編址等，都給單片機應用系統設計帶來布線復雜，線路板面積大，易引起emi和esd干擾等困難，這在一些比較復雜的應用系統是難以接受的。 -
There are six sub - modules in it : single - chip unit, data transfer unit, parallel data transfer / receive unit, serial data transfer / receive unit, system reset management and system power unit. this paper studies the design and realization of net interface module, mainly discusses design of data transfer unit ' s logic and the improvement of single - chip unit ' s software
論文首先從系統設計思想出發，對網路介面模塊的總體設計實現進行了研究，接著對作者主要研究的軟硬體分工協同設計中的軟體完善部分，邏輯設計部分，以及最後的邏輯測試、系統測試進行了重點論述。 -
Changing operations on the fly ? converting, say, a calculation of a matrix of numbers to a parallel - processing computation ? requires the relatively slow rewiring of connections between large blocks of transistors, not the individual elements ( gates ) that perform a processor ' s logic operations
若要以動態的方式改變操作（例如將數字矩陣的計算轉換為平行計算） ，得將大區塊電晶體間的連結緩慢地重新接線，而非直接改變處理器里執行邏輯運算的個別元件（邏輯閘） 。 -
However, in parallel with the maintenance effort, alcrohm plans to implement a new version of the application that will be accessible via a standard web browser, coupled with java server - side code and business logic
但是，與維護工作相比， alcrohm計劃實現一個新的應用軟體版本，這個版本能夠通過標準網路瀏覽器訪問，加上java語言的服務器端代碼以及業務邏輯。 -
( 3 ) based on principle analysis and simulation, the main parameters are obtained. and the hardware solution is proposed - parallel processing system with multiple dsp. ( 4 ) the design of the software used to control logic and timing is presented
（ 4 ）在硬體設計的基礎上，提出了在本系統中實現時序和邏輯控制的軟體（不包括正交波束形成演算法的實現）設計方案（包括系統中斷系統的設計和系統的bootload設計） 。 -
The goal we must achieve, when designing distributed parallel file system, was analyzed also. the thesis present the logic structure of dpfs, the structure and the flush strategy of the module of directory cache and its role in the read - write operation, duplicate table ' s physical and logical structure, the management and synchronization algorithm of the duplicate table, and the model and the management algorithm of the module of intelligent duplicate management. also the effects that dpfs exerts to the system reliability and the read and write performance compared to ext2 were analyzed
本文首先介紹了數據存儲的發展概況與新的需求，分散式文件系統對其發展的重要影響以及設計分散式文件系統需要考慮的各種問題；然後分析了為滿足分散式并行服務器的功能需求， dpfs應實現的目標；接著介紹了dpfs設計的總體邏輯結構，目錄緩存管理模塊的結構設計、刷新策略以及該模塊在文件讀寫重定向中的作用，副本表的邏輯、物理結構、對其緩存的管理和同步演算法的實現，以及副本智能管理的設計模型及其管理演算法的設計與實現，還分析了dpfs對系統可靠性的影響以及在讀寫文件時與ext2文件系統性能的比較。 -
In order to support the combination of behavior models and plan expression effectively, we extend the branching - time logical cognitive model based on interval - time logic, and implement the description of combined behaviors in branching - time logic and time constraining on parallel behaviors in planning
為了能夠直觀、有效地支持行為模型的組合和規劃的表示，論文基於區間時序邏輯對分枝時序邏輯認知模型進行了擴展，實現了對分枝時序邏輯中組合動作和規劃中并行動作時序約束的描述。 -
Based on analyzing the development and tendency of interface technique, the generalized interface is presented in this paper, which is following the design principles - high speed, convenience, high reliability, cheapness. this interface makes the switching input / output and analogue input / output to use the same enhanced parallel port by using the in - system programmable logic device - isp1032e
本文在分析介面技術的發展歷史及發展趨勢的基礎上，本著順應介面發展趨勢以及高速、便用、可靠、經濟等設計原則，設計開發了基於計算機并行口epp工作模式及在系統可編程邏輯器件isp1032e的開入、開出、模入、模出四路復用計算機并行口的通用介面。
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