parasitic capacitance 中文意思是什麼

parasitic capacitance 解釋
寄生電容
  • parasitic : adj. 1. 寄生的，寄生動[植]物的；寄生體的，寄生質的；（疾病）由寄生蟲引起的。2. 寄食的；奉承的。adv. -cally
  • capacitance : n. 【電學】電容；電容器。
  1. A lcc multi - resonant ( mr ) network is added to the traditional three - level converters to realize zvs. the unique arrangement of a multi - resonant network results in absorption of all major parasitic components hi the resonant circuit, such as transistor output capacitance, diode junction capacitance and transformer leakage inductance, which can eliminate parasitic oscillation in the converter

    它的優點在於諧振電容吸收了開關管和續流二極體的結電容，諧振電感吸收了變壓器的漏感，使得開關管和續流二極體都能在軟開關的條件下完成導通和關斷過程，消除了電路中的寄生振蕩。
  2. With the development of electronic technology in the field of high - frequency and high - power, power mosfet is gradually enhancing its important status in semiconductor apparatus and is being widely applied in power converters as switch. with the increasing of the operating frequency ( > 200khz ), the energy loss caused by parasitic capacitance will affect the efficiency of power transforming in converters. especially in the applications of high frequency power supply using mosfet as main devices ( the unit of frequency is mhz ), the energy loss caused by the switch process will badly affect its efficiency

    隨著電力電子技術進一步向高頻的大功率用電領域發展，功率mosfet在各種電力半導體器件中的重要地位日益顯著，使用功率mosfet作為開關器件的功率轉換電路也日益增多，但隨著器件開關頻率的提高（大於200khz ） ，由器件極間電容引起的能量損耗將會影響到功率轉換電路的能量傳輸效率，特別是在以mosfet作為開關器件的高頻感應加熱電源中（工作頻率可達兆赫） ， mosfet在開關過程中的能量損耗嚴重影響到電源的效率，因此如何減小開關器件的損耗提高高頻功率轉換線路的效率成為電力電子技術領域的重要研究課題之一。
  3. The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method

    該傳感器製作工藝簡單，靈敏度高，支撐梁採用u型，減小了刻蝕后的殘余應力，用玻璃作為襯底，減小了襯底和硅可動質量塊間的寄生電容，且把傳感器晶元和用ic裸片製作的介面電路集成在一起，提高了封裝密度，減小了傳感器系統的噪聲，為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。
  4. In the second part, we introduce the advantages of soi devices together with their corresponding mechanisms : free of latch - up effect, low parasitic capacitance, easy to form shallow junctions and so on

    論文的第二部分介紹了soi器件的優點:無latch - up效應，較低的源漏寄生電容以很容易形成淺結等，並對具體的機理作出了相應的解釋。
  5. This paper also presented the structure of soi bjmosfet and discussed and analyzed the advantages of this device by comparing with the bulk bjmosfet. its advantages are as fellow : no latch - up effect, better capability of resisting invalidation, much smaller parasitic capacitance, weaker hot - carrier effect and short - channel effects, and simpler technics, and so on

    通過與體硅bjmosfet比較，討論和分析了soibjmosfet的優點：無閂鎖效應、抗軟失效能力強、寄生電容大大降低、熱載流子效應減弱、減弱了短溝道效應、工藝簡單等。
  6. Semi - analytical integration approach in 3 - d parasitic capacitance computation with bem

    三維寄生電容邊界元計算的半解析積分方法
  7. Soi, namely silicon on insulator, device and ic have many advantages : low leak current, weak parasitic capacitance, low power loss, radiation hardness, and high integreted level

    Soi （ silicononinsulator ）器件及集成電路具有泄漏電流小、寄生電容小、功耗小、集成度高、抗輻射能力強等優點。
  8. So it is an important research in the field of the electronic technology to reduce the loss caused by the switching device and to improve the efficiency of high frequency power converters. this paper primarily focuses on the optimization of the mosfet parasitic capacitance so as to reduce the switching loss and improve the efficiency of power transforming in converters using mosfet as switch

    通過分析mosfet器件的開關特性，根據輸出電容c _ （ oss ）給器件引進的動態損耗來確定優化器件輸出電容西安理工大學碩士學位論文l變化曲線的目標函數，運用可行方向法求解帶約束條件的最優值，確定出優化的輸出電容人變化曲線。
  9. In this paper, the soi technology is applied to the integrated circuit fabrication. soi technology overcomes some disadvantages of bulk silicon because of its inherent structure. it has the advantages such as no latch - up effect, low parasitic capacitance, high transconductance, simple structure, high density and good anti - radiation

    Soi技術以其獨特的材料結構有效地克服了體硅材料的不足，它具有無閉鎖效應；漏源寄生電容小；較高的跨導和電流驅動能力；器件結構簡單；器件之間距離小；集成度高；抗輻射性能優良等優點。
  10. It details the ic design process and vlsi circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays

    它詳細規定了集成電路設計過程和超大規模集成電路電路，包括門陣列，可編程邏輯器件和陣列，寄生電容，及輸電線路的延誤。
  11. The results that increasing of bias current and shunted resistance and lowing critical current and connected inductance can decrease the transmission time are shown ; ( 4 ) a new type of circuit, ladder shape multiplayer jtl. structure is provided by author, thus output signal of rsfq circuits can be amplified before transfer to room temperature electronics system. it has highly gain of amplify relatively and the double peak structure are avoided through decreasing parasitic capacitance

    （ 4 ）針對目前超導與室溫介面電路的電壓放大器存在的「雙峰」和放大增益效率較低的不足，提出了一種全新的階梯式多層jtl電壓放大電路結構，較好的解決了以上的問題，通過初步的模擬分析證實，該電路的構思極負有創新性。
  12. The lna design method which absorbs the parasitic capacitance of esd is introduced and compared with the traditional design method

    同時提出了將esd的寄生電容吸收到lna輸入匹配網路中的設計方式，並與傳統的計算方式做了對比。
  13. 2. the control signals couple through the capacitance of the switches to the output, the dynamic error caused by the parasitic gate ? drain feedthrough capacitance is significantly lowered by the use of a reduced voltage swing at the input of the switches

    2 .差分開關的控制信號會通過晶體管的寄生電容耦合到輸出，從而影響dac的動態性能，設計中通過降低控制信號電壓的方法來解決這個問題。
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