parasitic inductance 中文意思是什麼

parasitic inductance 解釋
寄生電感
  • parasitic : adj. 1. 寄生的，寄生動[植]物的；寄生體的，寄生質的；（疾病）由寄生蟲引起的。2. 寄食的；奉承的。adv. -cally
  • inductance : n. 【電學】電感，感應現象；感應系數；（發動機）進氣。 inductance bridge 電感電橋。
  1. A lcc multi - resonant ( mr ) network is added to the traditional three - level converters to realize zvs. the unique arrangement of a multi - resonant network results in absorption of all major parasitic components hi the resonant circuit, such as transistor output capacitance, diode junction capacitance and transformer leakage inductance, which can eliminate parasitic oscillation in the converter

    它的優點在於諧振電容吸收了開關管和續流二極體的結電容，諧振電感吸收了變壓器的漏感，使得開關管和續流二極體都能在軟開關的條件下完成導通和關斷過程，消除了電路中的寄生振蕩。
  2. To make use of parasitic parameter to design the circuit : because parasitic inductance induced by packaging could not only influence the circuit characteristics, but also lead to a design failure, the inductor value needed in the circuit can be designed in the amplifier according to the size of parasitic inductance

    4 、利用寄生參數來設計電路。由於電路的封裝存在寄生電感，其不僅會影響電路的特性，而且可能造成電路設計工作的失敗，所以根據電路所需電感及其值的大小，將之有效的設計在放大器電路中。
  3. The results that increasing of bias current and shunted resistance and lowing critical current and connected inductance can decrease the transmission time are shown ; ( 4 ) a new type of circuit, ladder shape multiplayer jtl. structure is provided by author, thus output signal of rsfq circuits can be amplified before transfer to room temperature electronics system. it has highly gain of amplify relatively and the double peak structure are avoided through decreasing parasitic capacitance

    （ 4 ）針對目前超導與室溫介面電路的電壓放大器存在的「雙峰」和放大增益效率較低的不足，提出了一種全新的階梯式多層jtl電壓放大電路結構，較好的解決了以上的問題，通過初步的模擬分析證實，該電路的構思極負有創新性。
  4. However, some improvements have been made for the distributed rc model, the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region. so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance. according to this model, two cases, that is, cmos driving transmission line and interconnect line between chips have been analyzed

    對傳統的分佈rc模型進行了改善，但隨著互連向深亞微米級發展，寄生效應的影響尤其是電感的影響，必須考慮，因此建立新的rlc傳輸模型是很必要的，本文提出了這種新的互連模型，並對cmos驅動互連線和晶元之間互連兩種情況進行了分析，驗證了延時模型是可靠和精確的，並對延時的改善起到了指導作用。
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