phase clock 中文意思是什麼

phase clock 解釋
相位時鐘脈沖
  • phase : n 1 形勢，局面，狀態；階級。2 方面，側面。3 【天文學】（月等的）變相，盈虧；【物、天】相，周相，...
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  1. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  2. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  3. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  4. As concerning to the interference condition between different transmit / receive channels in the system, a detailed error analysis is given, and the clock and synchronization scheme is explicated. the measure adopted to enhance phase clock ' s precision is explained

    本文對超聲相控陣系統中各通道發射/接收的相干條件進行了詳細的誤差分析，闡明了本系統採用的時鐘和同步方案，以及改進相控陣時鐘精度的方法。
  5. Fist, quick bit synchronization. the common methods are relative synchronization, multi - phase clock sample and so on

    第一，快速比特同步。常規的方案有相關同步法和多相位時鐘采樣法等。
  6. Clock phase diagram

    直角坐標矢量圖
  7. The paper first reviews the research background and actuality of the filter " s design in china and other country, introduces the meaning of the project and the work of the paper, narrates the theory of the switched - capacitor network and the basic switch building blocks, analyses the related factors of the design of sc filter. such as the selection of the architecture, the trade off of the opamp " s gain, bandwidth, phase margin, slew rate and setting time, the effect of the switch " s on resistor, how to reduce the charge injection and the clock feed - through, the power consumption and the selection of the sampling frequency and so on

    本文首先回顧了濾波器設計的國內外研究背景和現狀，介紹了本課題提出的意義以及本文的主要工作，論述了開關電容網路原理和基本開關模塊，分析了開關電容濾波器設計的相關因素：電路結構的選擇，對運算放大器設計中高增益、寬帶寬、相位裕度、轉換斜率和建立時間等的折中考慮，開關的打開電阻對電路的影響，開關電容電路中怎樣減少電荷注入和時鐘饋通，以及整個電路的功耗問題和采樣頻率的選擇等。
  8. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法，並在me演算法基礎上進行改進，創造性的去掉了縮短碼解碼中的校正環節，糾正了有關論文中的不當論述，並將rs解碼模塊進行了參數化設計，同時也將rs解碼的規模縮小了20 ；克服了多時鐘設計中的信號完整性難題，在沒有增加模塊面積的條件下，大幅降低數據的相位摘要抖動，首次引入鎖相環來調整速率。
  9. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  10. The 33220a external frequency reference lets you synchronize to an external 10 mhz clock, to another 33220a, or to an agilent 33250a. phase adjustments can be made from the front panel or via a computer

    33220a外部頻率基準使您能同步于外部10mhz時鐘另一臺33220a ，或agilent33250a .相位調整可從前面板或通過
  11. This paper gives a time - synchronization technique bases on gps time service signal which is used in broad band seismic recorder 。 by world coordination time offered by gps - - utc ( usno ), adjust local clock base on gps signal, gain high nicety clock signal, clock precision reachs 10 - 6 。 this clock is the time source of broad band seismic recorder, bring the whole seismic recorder works in same time base. 1pps time base with high stability can be used as in - phase, spring, time and start - stop of every collection mode, while the scale under second make a precise time mark to receive data of broad band seismic recorder

    針對接收機中gps信號的噪聲進行kalman濾波軟體處理， kalman濾波可以對gps信號與本地晶振時鐘的時差數據在大噪聲中進行平滑，在較短時間內估計出高精度的時差數據。系統消除了gps秒脈沖信號的ms級隨機誤差，把晶振秒脈沖的長期穩定度鎖定到gps信號的穩定度上;在gps信號失效時給出了可行措施，能夠保證在任何情況下產生一個穩定、高精度秒脈沖信號，誤差在1 s內。
  12. The adc aperture jitter must be minimal, and the sampling clock generated from a low phase - noise quartz crystal oscillator

    Adc的孔徑抖動必需盡可能的小，而且要使用低相位噪聲的石英晶體振蕩器作為采樣時鐘發生器。
  13. Aiming at the scheme of the signal electromagnetic environment simulator of the wireless communication system, the mission of this project is to design and realize twenty - four frequency synthesizers, which must meet high expectation for the phase noise characteristic and the spurious repression characteristic of the output clock signal. these frequency synthesizers provide the moving of the basic signal generating modules to radio frequency with stable inspiring source

    本課題的任務是針對通信信號電磁環境模擬器系統的方案要求，設計實現24個（頻率分佈在260mhz 1430mhz之間）對輸出時鐘信號的相位噪聲特性、雜散抑制特性等要求都很高的頻率合成器，為基本信號生成模塊到射頻的搬移提供穩定可靠的激勵源。
  14. Although ranging is adopted, certain phase shifts still exist between bit flows from onus to olts. therefore, fast synchronization must be applied to synchronize the receiving clock of olt to the bit flow being received from a certain onu

    雖然採用了測距技術，但是各onu到達olt處的比特流仍存在一定的相位漂移，所以必須採取快速同步的技術，將olt的接收時鐘同步到當前所接收的、來自某一onu的比特流。
  15. A multiple - stage dynamic phase adjustment method between source synchronization driving clock and date is proposed ; it fits different operation frequencies and improves the system stability 6

    提出了一種源同步時鐘與數據相位的多級動態調節技術，從而適應不同的時鐘工作頻率，增加了系統的穩定性。
  16. The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit

    通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。
  17. The difference clock delay match technology adjusts the two channel ad analog clock phase and implements the two way ad uniformly - space sampling

    差分時鐘延遲匹配技術通過對兩路ad的采樣時鐘進行相位調整，實現了兩路ad的等間隔采樣。
  18. The clock used should be free from significant phase or frequency jitter

    應用的時鐘應沒有重大的周期或頻率的跳動。
  19. To speed up the synchronization, multi - phase clocks can be used in combination with the parallel sliding relevance searching method to select the best clock source

    為了提高快速同步的速度，可以利用多相位的時鐘，採用并行的滑動相關搜索方法，來選擇最佳時鐘源。
  20. The card designed in the dissertation applies analog channel switchover technology and difference clock match technology to implement intersection sampling the analog channel switchover technology branches off one channel signal and matches amplitude and phase

    模擬通道切換技術通過對一路輸入模擬信號進行分流及幅值、相位匹配保證了交叉采樣時兩路ad輸入模擬信號的一致性。
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