phase locking circuit 中文意思是什麼
phase locking circuit
解釋
相位同步電路-
It can be deduced from the characteristics of ilpll circuit that injection - locking bandwidth is not only related to the injection - locking bandwidth without feedback loop, but also related to the characteristics of frequency mixing, loop gain and the change of the loop phase. thus, the needed bandwidth can be obtained by adjusting the loop parameters. and the phase noise characteristics are mainly determined by loop transmission factor
由ilpll電路特性的推導得出:注入鎖定帶寬不僅跟開環時的注鎖帶寬有關，而且與混頻特性、環路增益以及環路相位變化相關聯，可以通過調節環路的參數得到所需帶寬;相噪特性主要由環路傳輸因子決定，可以通過調節環路濾波得到比開環注入鎖定相噪更優的特性。 -
And the new circuit structure for improving the locking range, that is, injection - locked phase - locked loop circuit ( ilpll ) is introduced into the millimeter wave circuit
在此基礎上，結合注入鎖定和環路鎖相原理，在毫米波頻率源中引入了一種新型的展寬帶寬的電路結構環路注入鎖定鎖相電路（ ilpll ） 。 -
Design and realization of a single - chip digital phase - locking frequency - multiplier circuit
單片數字鎖相倍頻電路的設計與實現 -
The paper analyzes in detail the characteristics of this circuit in the aspect of locking range improvement and its merits in the aspect of phase noise, and designs the ilpll circuit in the form of ka band cavity structure and verifies its characteristics
文章詳盡分析了此電路在展寬帶寬方面的特性和相噪的優越性，設計了ka波段腔體結構形式的ilpll電路並驗證了其特性。 -
Thus, the better phase noise can be obtained by adjusting the loop wave filtering. through experimental verification, the locking range of the designed ka band ilpll circuit is 2. 5 times to 9 times widened and the phase noise, compared to that without feedback loop, is reduced by 4dbc @ 1khz and the noise can be reduced by adjusting the loop wave filtering and
經過實驗驗證，設計的ka波段ilpll電路的鎖定帶寬拓展了2 . 5倍以上，最大處達到9倍左右;相噪與開環注鎖相比降低了4dbc @ 1khz ，且可以通過調節環路濾波和注入功率來降低噪聲。
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