pipelined 中文意思是什麼
pipelined
解釋
流型-
According to research of redundant signed digit ( rsd ) calibration theory of pipelined adc, a novel out of range detection rsd technique is provided. when input signal is out of the adc ’ s range, the technique can detect this situation and the wrong output word is avoided
然後，在深入分析冗餘位演算法的基礎上，提出了新型的校正演算法，針對傳統演算法不能判斷信號超出adc處理范圍的不足，增加了溢出判斷功能，既能有效校正比較器的失調，又防止了信號溢出時的誤碼輸出，保證了系統的性能。 -
Trigonometric function generator based on pipelined cordic
演算法的三角函數發生器 -
Task assignment algorithm for pipelined computing in grid
網格中流水式計算的一種任務指派演算法 -
In this paper, a new architecture of hardware decoder based on the modified euclidean algorithm ( mea ) is provided, and it is called the fprme ( fully - pipelined recursive modified euclidean ) decoder
本文基於修正的歐幾里德演算法（ mea ）設計了一種新的硬體解碼器實現結構，稱其為fprme （ fully - pipelinedrecursivemodifiedeuclidean ）解碼器。 -
In this paper, the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced, and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm, reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail. based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented. a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre - quency
本文簡要介紹了有限域基本運算的演算法和常用的rs編碼演算法，詳細分析了改進后的euclid演算法和改進后的bm演算法，針對改進后的bm演算法提出了一種流水線結構的譯碼器實現方案並改進了該演算法的實現結構，在譯碼器復雜度和譯碼延時上作了折衷，降低了譯碼器的復雜度並提高了譯碼器的最高工作頻率。 -
Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail
基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。 -
Considering that the time of image preprocessing is the key fact affecting the performance of real time, it designs hardware circuits for median filtering and edge detection. the pipelined and parallel processing methods are used in circuit design to raise processing speed and save hardware resource
針對影響系統實時性最大的圖像預處理部分，在fpga設計中，實現了預處理的中值濾波和邊緣檢測硬體電路，將流水線處理技術和并行處理等技術應用到電路設計中，提高了處理速度，節省了硬體開銷。 -
After comparing the various types of a / d structures and their advantages and disadvantages, this project adopts pipelined structure and processes the voltage of the analog input. it is structured in 10 identical stages cascaded, each of which quantizes the analog signal from the previous stage and outputs one bit the digital code as well as the residue signal to the next stage
它採取10個相同的處理單元級連，每個處理單元對所輸入的模擬信號進行量化，輸出一位數字信號，並把經該級處理后剩下的量化噪聲信號傳入下一處理單元，如此下去，直至最後一個處理單元。 -
For general nonlinear time series ( not - season time series ), on the foundation of pipelined recurrent neural network, bfgs ( broyden - fletcher - goldfard - shannon ) is introduced in, so a study algorithm based on bfgs is put forward
對於一般的非線性時間序列（非季節時間序列） ，我們在現有的管道神經網路基礎上，把bfgs演算法引入到該網路的學習中，提出了基於bfgs的管道神經網路學習演算法。 -
Bsram burst pipelined synchronous static ram
突發式管道同步靜態存儲器 -
Moreover, regulating the signals from the sub - detectors of besiii is the key technique that could determinates whether trigger system discriminates the good events. this paper describes a pipelined digital programmable delay module, which is to be used in the global trigger, designed as a single width 6u standard vme module. two main method are used in the preliminary design : one utilizes shit register and multiplexers, which is simple and reliable
在預研製過程中，使用了兩種可編程的延遲方法並對比了這兩種方法：一種是利用移位寄存器與多路選擇器串聯來實現可編程的延遲，此方法簡單、可靠性強；另一種則是利用雙口ram具有的獨立的讀和寫地址線，在設計中使讀、寫地址間距可調來實現可編程延遲。 -
A speed analysis methodology for pipelined a d converters
轉換器的速度分析方法 -
It has a macroblock - level pipelined structure which consists of mv predictor unit, reference fetch unit and pixel interpolation unit
該結構由3個流水階段組成： mv預測模塊參考數據獲取模塊分數像素插值模塊。 -
Cordic algorithm is also easily pipelined, it is possible to achieve high - performance in computation sys - tems
而且cordic演算法也容易流水線實現，可以在計算系統中的高速進行。 -
Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products
討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。 -
The contribution of this dissertation includes : ( 1 ) a register sensitive unrolling ( rsu ) algorithm is presented, which evaluates unrolling factors considering register pressure to allow more loops to be software pipelined ; ( 2 ) a stacked register allocation ( sra ) algorithm is presented to allocate free stacked registers to variants requiring static registers
本文的主要貢獻包括以下幾個方面： （ 1 ）提出了一種寄存器敏感的循環展開因子（ rsu ）演算法。該方法通過寄存器壓力的分析，重新計算循環展開因子，避免了過度展開而導致的寄存器壓力過大問題，從而盡可能地保證軟體流水的順利進行； （ 2 ）提出了一種堆棧寄存器分配（ sra ）演算法。 -
Maximum time difference pipelined arithmetic unit based on cmos gate array. j. computer science and technology, 10 ( 2 ), 1995, ( with z. tang )
大規模并行處理系統的反圖互連網路。香港?北京國際計算機會議論文集，北京， 1997 ， （與韓承德等合作） ， （特邀報告） 。 -
A maximum time difference pipelined arithmetic unit based on cmos gate array. j. computer science and technology, 10 ( 2 ), 1995, ( with z. tang )
大規模并行處理系統的反圖互連網路。香港?北京國際計算機會議論文集，北京， 1997 ， （與韓承德等合作） ， （特邀報告） 。 -
It ’ s critical path delay is very little, and it operates in the fully - pipelined continuous decoding manner
它關鍵路徑延時很小，並且為全流水線連續解碼工作方式。 -
The hiberarchy of software simulation are function verification and cycle - accurate behavioral simulation. the latter are required for make up the model of pipelined processor
對于模擬的要求，有基於功能驗證和周期精確兩個層次，周期精確需要實現流水線級系統結構模擬。
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