pnp transistor 中文意思是什麼

pnp transistor 解釋
pnp晶體管
  • pnp : 菲律賓國家警察
  • transistor : n. 【無線電】晶體(三極)管;晶體管[半導體]收音機。 a transistor radio 晶體管[半導體]收音機。
  1. Semiconductor discrete device. detail specification for pnp silicon low - power transistor for type 3cg110gp gt and gct classes

    半導體分立器件gp gt和gct級3cg110型pnp硅小功率晶體管.詳細規范
  2. The design and analysis of vertical pnp transistor was accomplished through the relationship between carriers lifetime of epitaxy layer and current gain, rate of surface combination and leakage current, carriers lifetime of epitaxy layer and switch speed

    從外延層載流子壽命與晶體管放大倍數,表面復合率與漏電流,以及外延層載流子壽命與晶體管開關速度等方面對于輸出級縱向pnp管進行了較為詳細的設計與分析,達到了電路中對輸出級縱向pnp管主要參數指標的要求。
  3. Npn or pnp transistor output using a reliable, adjustable response time

    使用npn或pnp晶體管的可靠輸出,可調節的響應時間
  4. Detail specification for electronic components. case rated bipolar transistor for silicon pnp low - frequency amplification for type 3cd 507

    電子元器件詳細規范. 3cd507型硅pnp低頻放大管殼額定的雙極型晶體管
  5. The temperature sensing circuit adopts current - output mode taking pnp substrate transistor as temperature sensing device. according to the theory of the bgr, ptat and ctat can be generated from the circuit, and the former one is regarded as the initial signal which correlating to the temperature

    溫度傳感電路以襯底pnp型bjt作為感溫元件,採用電流輸出模式,按照帶隙基準原理獲得與絕對溫度成正比( ptat )電流以及與絕對溫度成反比( ctat )電流,並以前者作為與溫度相關的原始電信號。
  6. A silicon self - aligned technology was achieved by using a smart power integrated technology to get high power of the circuit. vertical pnp transistor whose base is epitaxy layer was used as output. the collector of the vertical pnp transistor was set on the back of the chip with low resistance p + substrate as ohm contact

    在工藝中,採用了smart功率集成技術實現電路的大功率,基區是外延層的縱向pnp晶體管作為輸出,將集電極置於晶元背面,採用低電阻率p ~ +襯底作為歐姆接觸。
  7. Delay in three models a pattern of delay or closure of the extension opened pm, the choice ranging from 0. 1s to 5s dc output transistor sensor has dual npn pnp light diffuse reflectance sensor to regulate and control functions

    有三種延時模式一次使用模式,打開延時或關閉延時,選擇范圍從0 . 1s至5s dc傳感器具有雙重npn pnp晶體管輸出
  8. The dominance and properties of the cmos integrated reference were also described, and the research meaning was pointed out. related device theory and process model used in design were described. the temperature related model and the influencing factor of two active devices, subthreshold mosfet and pnp substrate transistor, based on cmos process were analyzed and compared, and pointed out that the pnp substrate transistor was more fit for being the temperature compensating device for bandgap reference

    闡述了設計中相關的器件理論與工藝模型,對cmos工藝下的兩種有源器件,即亞閾值工作狀態下的金屬場效應晶體管( mosfet )及襯底pnp雙極型晶體管( bjt )的溫度模型及其影響因素進行了分析和比較,指明襯底pnp雙極型晶體管更適合作為基準源的溫度補償元件。
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