processor interrupt 中文意思是什麼

processor interrupt 解釋
處理機岔斷
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  • interrupt : vt. 1. 阻止；妨礙；遮斷。2. 打斷（別人的話等）；中斷；打攪。3. 截斷。vi. 打擾，（別人談話時）插嘴。
  1. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  2. And this thesis also analyzed the characteristics of packet receiving interrupt handler and it ' s max interference on the other tasks on the same processor with lower priorities

    此外本文還分析了報文接收中斷處理程序的時間特性和它對節點上其它任務最大響應時間的影響。
  3. In the first step, the author introduces the rtxc real time operation system and illustrate in detail the boot code design of arm processor, secondly, the author offers a whole structure under this operation system and explains the function of this software in terms of four relative tasks, in which the signal processing module, interface interrupt processing module, system operation measuring and controlling module and rc & lc information processing module are illustrated at length

    先介紹了實時操作系統rtxc ，詳細闡述了arm處理器啟動代碼程序的設計，然後給出了在此操作系統下軟體設計的整體結構，分四個任務分別闡述此軟體功能，其中詳細介紹了信令處理模塊、介面中斷處理模塊、系統運行監測模塊和rc消息lc消息處理模塊。
  4. Code that the processor jumps to on receipt of an interrupt request

    使處理器跳轉到中斷請求接收的編碼。
  5. When an interrupt occurs, the current state of the processor is s * * ed and an interrupt service routine is executed

    當一個中斷發生，當前的處理器狀態被保存並且中斷服務程序開始運行。
  6. This paper, first, studies the performance and architecture of high performance processor pipeline, and the technology that used to deal with the correlation and interrupt in pipeline. the author takes part in study and design of pipeline of armp, which is a 32 - bit embed microprocessor

    本文首先研究了高性能處理器流水線的性能與結構以及對相關和中斷的處理等關鍵技術，作者作為設計人員參與研究並設計了32位嵌入式微處理器apmp的流水線。
  7. The simulation of the addressing mode provides the possibility for the instruction simulation, and the simulation of the interrupt, timer and serial port lets the simulator implement the functions of the interrupt, timer and serial like a processor, and the program control simulation provides the possibility for running the program. this function is also the base for debugging program, which can set step running mode, set break points by using this program

    尋址方式的模擬為指令的模擬提供了可能，中斷、定時器和串列口的模擬使模擬器可以象處理器一樣完成中斷功能、定時功能和串列通訊功能，程序控制的模擬為程序運行提供了可能，這一功能又是調試程序的基礎，通過這個程序程序可以單步執行，設斷點執行。
  8. When an interrupt occurs, the current state of the processor is saed and an interrupt serice routine is executed

    當一個中斷發生，當前的處理器狀態被保存並且中斷服務程序開始運行。
  9. If your timing requirements are modest, a simple task, or even interrupt routine, might well be more efficient in both code space and processor cycles

    如果你的定時要求適當，一個簡單的任務，甚至是中斷處理程序，可能在代碼空間和處理周期上都更加有效。
  10. Processor dependent interrupt

    處理機相關的中斷
  11. Processor error interrupt

    處理機誤差岔斷
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