pulse-delay circuit 中文意思是什麼

pulse-delay circuit 解釋
脈沖延遲電路
  • pulse : n 1 脈搏;有節奏的跳動;【動物;動物學】脈沖(波);脈動。2 意向;傾向。3 【音樂】拍子,律動。vi ...
  • delay : vt 延遲,拖延,耽擱。 We ll delay the party for two week 我們要把會期延遲兩周。 The train was del...
  • circuit : n 1 (某一范圍的)周邊一圈;巡迴,周遊;巡迴路線[區域];迂路。2 巡迴審判(區);巡迴律師會。3 【...
  1. The pulse width trigger circuit, trigger delay circuit are discussed. and a new kind of peak detection module which is implemented by verilog hdl in fpga and greatly enhances the performance of catching glitch is discussed in the dissertation. the waveform recorder function accomplished in the scopemeter can test, monitor slow analog signals and record the characteristic value of signals continuously for a long time

    本文討論了脈寬觸發電路和觸發釋抑電路的實現,採用veriloghdl在fpga中實現了一種峰值檢測模塊,提高了示波表的毛刺捕捉能力,設計的波形記錄( recorder )功能模塊能夠對輸入的模擬信號進行長時間連續不斷的采樣量化,並記錄波形數據和及時送顯示。
  2. The design of the circuit ? key parameters including pulse width in the level shifter part and delay time of the filter circuit, and the necessity to add a limiting current resistor at source the ldmos were emphatic analyzed. author finished the design of each sub - circuit

    對電路關鍵參數高低壓電平位移脈沖寬度、高端濾波電路濾波寬度的設計及在ldmos源端加入限流電阻的必要性進行了重點分析,完成了各單元電路的設計。
  3. To solve this problem, quick range measurement technology was researched based on the method of propagation delay and working principle of cpld. a time measurement circuit with an accuracy of ? 0. 2m was designed and accomplished. it could finish the whole measurement process in 80ns after the bounced pulse was received

    針對該問題,基於傳遞延時插入法和cpld的工作原理,對快速測距技術進行了研究,研製了一種能實現收到回波脈沖后80ns內完成測距,測距精度0 . 2m的計時電路,並將該電路集成於一片可編程邏輯器件中,減小了電路面積和功耗,增強了抗干擾能力。
  4. First, delay window is used to reduce influence of pulse disturbance and signal amplitude to measurement result. second, according to the feature that width of receiving signal is wider than disturbing signal, width differentiation circuit is utilized to distinguish receiving signal and disturbing signal. third, most of digital circuits are integrated into isplsi ( in system programmable large scale integrated chip ) 1032 so as to simplify design and to develop the stability and reliability of the system

    關于提高系統的穩定性和可靠性問題:一是採用了延遲窗口接收技術,以盡可能減小干擾脈沖對測量結果的影響;二是根據接收信號脈寬比干擾信號脈寬要寬的特點,採用脈寬鑒別電路來鑒別接收信號;三是用可編程大規模晶元isplsi1032對系統大部分的數字電路進行了集成化設計,達到既簡化電路設計、又提高系統穩定性可靠性的目的。
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