sampling channel 中文意思是什麼

sampling channel 解釋
采樣道
  • sampling : n. 1. 取樣（品），取標（本）〈指行動或程序〉。2. 樣品，標本。3. 剽竊拼湊歌曲。
  • channel : n 1 水路，水道，渠，溝；海峽；河床，河底。2 （柱等的）槽，凹縫；【機械工程】槽鐵，凹形鐵。3 〈比...
  1. Chapter two is data sample of system. it will discuss the data conversion theory, 24bit e - a data conversion, mux - channel switch sampling technology, and emc design. among them, we will introduce the principle and application of ads 1251, application of photomos technology in mux - channel switch sampling, and emc design with hardware and software of gas feed controller, which has good performance in reliability

    第二章介紹系統的數據採集，該部分包括24bit -采樣原理、多路信號切換採集技術和電磁兼容設計，其中，主要介紹了ads1251晶元的工作原理和應用， photomos技術在多路信號切換采樣中的應用，以及配氣控制器在硬體、軟體等方面所做的電磁兼容設計，通過這些設計使得系統具有很好的穩定性和抗干擾性。
  2. First, the structure of sdr and the physical - channel of td - scdma are expounded, then software and hardware models of the terminal receiver, which use the sdr structure of wideband and bandpass sampling in if ( intermediate frequency ), are put forward

    首先對軟體無線電的組成結構和td - scdma物理通道進行了闡述，在此基礎上提出了基於寬帶中頻帶通采樣軟體無線電結構的td - scdma終端接收機的軟硬體模塊設計方案。
  3. High precision ad chip is used for intermediate frequency data sampling and fpga of virtex - series is used for the implementation of intermediate - frequency orthogonal system, which includes the sequencing control design for mult - channel radar system with verilog, the application of ip core of digital filter and fifo, as well as the communication control module with dsp. as the master control part, the software programming for the communication between dsp and fpga is designed. the experimental result with hardware circuit shows the design is valid and practical

    採用高精度的adc晶元完成中頻采樣，通過virtex -系列fpga設計中頻正交系統，主要包括通過verilog語言實現多路雷達中頻接收的時序控制，通過濾波器ip核實現濾波器的設計，以及利用c語言實現dsp的通訊控製程序設計。並給出了fpga在資源和速度上一些優化的方法，調試過程中影響中頻正交接收性能測試的因素。
  4. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  5. Investigations of the raw material in hard - coal - mining ; channel sample ; sampling and schema of tests

    硬煤礦的原材料勘察.礦槽試樣.取樣及試驗大綱
  6. Measured for pressure is based in zero dead time parallel acquisition technology. one board has been 4 channels. one channel has been 100ksps sampling rate and 20mv 10v input signal range ( 7 scopes selectable )

    對壓力的測量基於多通道無間隔并行採集技術，單模板可實現4通道并行採集，每通道采樣率100ksps ，信號輸入范圍20mv 10v （七擋可選擇） 。
  7. Combining with the practical project, the development of an instrument for multi - channel harmonic detection and analysis were described in the third chapter, including the system structure, hardware and software of the device. then the technology of multi - channel data gathering was discussed, and some key techniques have been presented including high precision 、 high speed sampling of the voltage and current, fast flourier transform ( fft ), data compression and storage techniques, planar graphic fitting, three dimensional graphic projection, multithreading and the computer graphics techniques

    第三章結合多通道諧波監測及故障錄波一體化裝置的研製這一課題，介紹了裝置的體系結構和硬體、軟體構成，詳細介紹了在裝置研究過程中所提出的關鍵技術，主要包括電流電壓信號高精度、高速采樣技術，快速傅立葉變換fft 、數據壓縮存儲技術，多線程技術，二維圖形擬合、三維圖形投影技術及海量存儲技術，計算機圖形技術等。
  8. Each channel has independent synchronization and two powerful digital signal processing chips. one chip performs all the synchronization and sampling computations, while the other does the fast fourier transform of current and voltage signals sampled with 18 bit resolution. both current and voltage have separate but fully synchronized a d waveform capture sections

    就信號分析能力而言， 2503ah系列的最大特點是速度和精度，各通道均獨立同步及擁有兩片數字信號處理器晶元，當一晶元執行全部同步與取樣運算時，另一晶元則為已取樣的電流與電壓信號以真實18位解析度進行速傳立葉變換，電流與電壓具分離但完全同步的a d波形捕捉部份
  9. Use 24bit dac 96khz to process audio by sampling frequency and output perfect sound quality by 5. 1 channel double decoding. no need to connect to the external decoding amplifier

    專業的音頻視頻輸出端子，自動制式pal ntsc制式兼容av監視器，支持家用電視輸出
  10. The project is to develop the 100mhz wideband digital storage oscilloscope ( wdso ) ， typical performance character : input signal - 3db bandwidth is 100mhz, real time sampling frequency is 20msa / s, equivalent sampling frequency is 10gsa / s, resolution is 8bits, dual signal channel, and delicacy is 5mv 5v div per channel ， time sweep velocity is 2. 5ns - - 5s div 。 so the project is provided with higher performance - to - price ratio, stronger competitive capacity in market and widest applied foreground at the area of wdso

    本次課題的具體目標是實現100mhz帶寬的數字存儲示波器正樣機的研製，具體主要性能指標達到最高實時采樣率20msa / s 、等效采樣率10gsa / s 、被觀測信號3db模擬帶寬達100mhz 、采樣數字解析度8bit ；雙通道，幅值靈敏度： 5mv 5v div ，掃速2 . 5ns - - 5s div 。該方案具有較高的性價比，較強的市場競爭力和廣闊的應用前景。
  11. The project is to develop the 100mhz bandwidth, equivalent sampling frequency is 1g / sa, resolution is 8bits, dual signal channel, and delicacy is 5mv - 100v / div per channel, time sweep velocity is 20ns - - 5s / div digital storage oscilloscope ( dso ) 。 achieved equivalent sampling is innovative and main content of the project

    本設計的具體目標是實現帶寬為100mhz ，等效采樣率為5gsa / s ，采樣數字解析度為8bit ;雙通道，幅值靈敏度為5mv 100v / div ，時基為: 10ns 5s的手持式數字存儲示波器.等效采樣的實現是本設計的創新點和主要研究內容
  12. The main content and creative work in this dissertation include : ( 1 ) design a high precision sampling circuit based on a dual channel adc ad10242 to provide data for the whole system

    本文完成的主要工作和創新之處有: （ 1 ）基於雙通道模數轉換器ad10242設計高精度數據採集電路，為整個脈壓系統的工作提供必要的條件。
  13. In the part of platform designing, proper peripheral chips are chosen according to the audio signal format. and how to achieve channel synchronization in the receiving part is an important aspect of wireless transmission system. in order to solve this problem, three algorithms are used ; those are scramble / descramble, improved over - sampling, and frame synchronization protocol

    在硬體驗證平臺的設計部分，文章根據音頻信號的特點選擇了適當的外圍晶元，並且針對無線傳輸接收端的同步問題，採用了三種演算法來減少失步現象，即擾碼/解擾演算法，改進型的過采樣演算法，以及幀同步協議。
  14. Single chip needs too much time to calculate and we ca n ' t detect power quality real time for example, and the sampling rate must synchronize the signal frequency. when sample multi - channel signal in turn, it must have time delay between two samplings, so the phase angle difference between each channel signal is ca n ' t be avoid and so on. those problems must be solved

    本課題分析了目前電能質量的各種檢測方法，認為快速傅氏演算法（ fft ）是首選方法，但是基於定時采樣的fft計算會產生頻譜泄漏，為了減少這個泄漏需要進行加窗處理，這需要增加采樣數據，導致顯著增大計算量。
  15. Chapter three provides synchronization algorithms in dvb - t cofdm receiver, including symbol timing recovery, carrier frequency error estimation and sampling timing recovery. chapter four introduces some channel estimation algorithms based on interpolation in dvb - t receiver. five estimators are compared, in terms of mean - squared error both in rayleigh channel and ricean channel

    第三章首先討論了由於載波頻率偏差、符號定時偏差和采樣定時偏差對ofdm系統所造成的影響和干擾，然後針對dvb - t系統的cofdm接收機方案，分別給出了符號定時同步、頻率同步以及采樣鐘同步的實現演算法，並對它們的性能進行了分析模擬。
  16. Because limited by the sampling channel of transient electromagnetic measuring depth fieldwork curve ( generally 20 ~ 40 channels ), the smoothing degree of fieldwork curve is not very good, it make against the differential imaging treatment. in order to hold the continuous change characters of the curve and seek the voltage exactly, we use the thrice spline insert number function to reconstruct the fieldwork data ; 4

    ） t ； 3 .由於受瞬變電磁測深實測曲線取樣道的限制（一般為20 ~ 40道） ，實測曲線光滑程度較差，不利於微分成像處理，為了更好的把握曲線連續變化的特徵及準確求導，採用了三次樣條插值對實測數據進行重構;續
  17. This master degree thesis, based on the observing of developing actuality of on - site electrical apparatus monitoring technology, aims at overcoming the problems existing in former on - site monitoring system, such as unable to realize multiple channels sampling and hold, unable to carry out multiple channel programmable magnification, unable to monitor frequency, low pick up bits, external rom low speed data saving, inefficient data query method, inflexible debugging and installation, low precision etc. by introducing eda ( electrical design automation ) technology, we put forward a creative circuit design scheme, which can considerable updated the on - site monitor system

    本文根據電氣設備絕緣在線監測技術的發展現狀，針對以往在線監測數據採集系統存在的集成度低，不能實現多通路并行采樣，不能實現多通道同時程式控制放大，不能進行同步頻率監測，采樣位數較低，採用外部存儲器方式，對數據進行查詢的訪問方式，安裝調試不靈活等缺點，提出了應用現代微電子技術電子設計自動化（ eda ）技術實現對在線監測數據採集系統的改進。
  18. Hardware controller uses the at89c51 monolithic integrated circuit, a / d transformation uses 12 bit transformations chips max187, has completed the design of a front channel for sampling and processing the simulated signal

    其中硬體單片機採用at89c51單片機， a / d轉換採用12位轉換晶元max187 ，完成了模擬信號從采樣到處理的整個前向通道設計。
  19. A switch ic for analog signal processing is designed and implemented, which can fulfill the functions of sampling, weighting, controlling and summing of high frequency analog signals. the circuit consists of three parts : four channel analog switches, a voltage reference and the control circuitry. each analog switch is comprised of two high - transconductance n - mosfets with high w / l ratio, which realize the fine tuning and coarse tuning of the input signal respectively

    本文研究並設計了一種可對高頻信號進行取樣、加權、控制、疊加的模擬信號處理丌關集成電路，它包括模擬開關、電壓基準源和移位寄存器三個功能模塊，通過兩個高寬長比的高跨導nmos晶體管實現權值的粗調和微調。
  20. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
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