sampling clock noise 中文意思是什麼
sampling clock noise
解釋
采樣時鐘帶來的噪聲-
To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
為此,時鐘信號應該盡可能地與電路中強噪聲的部分隔離開,例如數字電路。 -
The adc aperture jitter must be minimal, and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔徑抖動必需盡可能的小,而且要使用低相位噪聲的石英晶體振蕩器作為采樣時鐘發生器。 -
The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies
在第三章討論的采樣時鐘抖動對信噪比和有效位性能的影響在欠采樣應用中因為更高的輸入信號頻率顯得更有戲劇性。
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