shift clock 中文意思是什麼
shift clock
解釋
變換時鐘-
To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named det ( double - edge - triggered ) shift register is proposed
摘要從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。 -
Then, we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock
接著，從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。 -
High - qualified designers and engineers of chaowei are able to provide various high - qualified design services such as ic software program, circuit board, product appearance, products structure, and product package, etc. the factories directly under chaowei have advanced production abilities including mould making, inection moulding, surface spray - painting, silk - screening, shift - screening, smt, welding and assembling, quartz clock core production, and quality check and assurance. chaowei held many design patents and utility model patents, at the same time, national clock and watch quality certification, national technical supervision bureau certification, usa fcc and astm security authentication, canada ic, and euro ce are achieved, the rich experience in oem and odm can ensure high quality products and professional service
超維公司擁有一批高素質的專業設計師和工程師，有能力為國內外客戶提供包括ic軟體編程線路板設計產品外觀設計產品結構設計產品包裝設計等多方面高水準的設計服務超維的直屬工廠則擁有模具製造注塑成型表面噴漆絲印移印smt焊接裝配石英鐘機芯製造品質檢驗測試等先進的生產能力超維公司的產品擁有大量的外觀設計專利和實用新型專利，同時獲得了國家鐘表質量檢驗中心的合格證書國家技術監督局檢驗合格證書美國fcc認證和astm安全認證加拿大ic認證歐盟ce認證。 -
They will be on round - the - clock shift duty
平日及假期均有隊員二十四小時輪值候命。 -
For example, a student may be too nervous to sleep the night before the examination. sometimes your " internal clock " becomes confused if you work on shift or travel to another country with different time zone
人體的生理時鐘受到擾亂，例如要輪班工作，或是往外地旅遊之人士，會由於兩地的時差關系而擾亂人體的生理時鐘，引致失眠。 -
If no measures are taken, the serious basic - line - shift as well as the loss of chip clock and the difficulty of the data recovery will be introduced in the optical receiver, which causes the communication to go along abnormally
如果不採取任何措施，會給光接收機帶來嚴重的基線漂移，同時會引起碼時鐘丟失和碼元恢復困難等一系列問題，導致通信無法正常進行。 -
Evening shift works 12 hours continuously, subsidiary standard is 4. 4 yuan, the breakfast allowance cost of the morning shift worker that goes to work before 5 o ' clock is 0. 8 yuan
夜班連續工作12小時的，津貼標準為4 . 40元， 5點前上班的早班職工的早餐補助費為0 . 80元。 -
To the satisfaction of workers from night shift, they offer round - the - clock service
使夜班下班工人滿意的是他們提供通宵服務。 -
Night shift workers get used to sleep the clock round on weekends
輪夜班的工人，周末常不分晝夜地睡。 -
Error : vhdl error at shift. vhd ( 18 ) : can ' t infer register for signal " q [ 3 ] " because signal does not hold its value outside clock edge
每個時鐘上升沿移位一次，按您說的要加循環吧.移位一次沒問題，加上循環就不行了，有錯誤 -
The worker that evening shift job comes off work later to 24 o ' clock, subsidiary standard is 3. 4 yuan
夜班工作到24點以後下班的職工，津貼標準為3 . 40元。 -
And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper
為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間，又要達到單周期完成一條運算指令的吞吐量指標，本文提出對ex級進行可伸縮超流水擴展的思想，提出並實現了一種高性加比的切換控制方案。 -
The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit
通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。 -
Calculation for the data from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。 -
Calculation for the data resulted from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。
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