synchronization bit 中文意思是什麼

synchronization bit 解釋
數元同步
  • synchronization : n. 同時；同時性；【物理學】同步，同期；【電影】同期[步]錄音，配音譯制。
  • bit : n 1 少許，一點兒，一些；（食物的）一口，少量食物。 〈pl 〉 吃剩的食物；小片。2 〈口語〉一會兒，一...
  1. Each time slot of the uplink frame contains a byte overhead, whose guard time is used to keep slight phase shifts from impairing the signal. the prepositive bit pattern is used for synchronization capture

    在上行幀的每個時隙里有位元組開銷，其防衛時間用於防止微小的相位漂移損害信號，前置比特圖案則用於同步獲取。
  2. 8b / 10b encoding adapt the characteristic of fiber channel very well, it has been used in high - speed fiber transmission broadly. it avoids the appearance of continuous “ 1 ”, “ 0 ”, offers plenty of bit synchronization time information, enhances the stability of output light signal, reduces interference between signals and offers proper redundancy to check error through transmission

    它避免了連「 1 」 、連「 0 」碼的出現，提供了豐富的位同步定時信息，減少了直流基線漂移，提高了光輸出功率的穩定性，減少了高低頻分量，改善了信號間的串擾，提供了適當的冗餘，便於檢測系統傳輸中帶來的錯誤。
  3. This thesis researched the time synchronization method for 2d - ss system, and deeply discussed the bit error rate ( ber ) performance of multicarrier domain spread spectrum chip - level differential detection ( mc - ss - cldd ) in the presence of multi - user interference

    本論文從多載波擴頻通信系統出發，提出了廣義二維擴頻系統的同步演算法，並對多載波頻域擴頻碼片級差分檢測技術在多用戶情況下的系統性能進行了深入的研究。
  4. Bit synchronization circuit design for digital communication system

    數字通信系統位同步電路設計
  5. Fist, quick bit synchronization. the common methods are relative synchronization, multi - phase clock sample and so on

    第一，快速比特同步。常規的方案有相關同步法和多相位時鐘采樣法等。
  6. Only when olt receives the first few bits of the uplink burst of onu and achieves the bit synchronization can the onu signal be restored

    Olt必須在收到onu上行突發的前幾個比特內實現比特同步，才能恢復onu的信號。
  7. When receiving the uplink frame, olt searches the synchronization pattern to quickly capture the phase information of code flows and achieve the bit synchronization. based on the delimitation pattern, it then delimits the atm cell to accomplish the byte synchronization

    Olt在接收上行幀時，搜索同步圖案，並以此快速獲取比特流的相位信息，達到比特同步；然後根據定界圖案確定atm信元的邊界，完成位元組同步。
  8. In the new model, the legitimate partners can control the error bit rate of the eavesdropper ' s channel by adjusting their virtual binary symmetric channels. when our new model is implemented, the problem of receiving synchronization of the partners will not occur

    在該模型中，通信雙方使用虛擬的二元對稱通道來控制竊聽方接收通道的誤比特率，而且使用該模型也不存在信息接收同步的問題。
  9. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  10. Each channel has independent synchronization and two powerful digital signal processing chips. one chip performs all the synchronization and sampling computations, while the other does the fast fourier transform of current and voltage signals sampled with 18 bit resolution. both current and voltage have separate but fully synchronized a d waveform capture sections

    就信號分析能力而言， 2503ah系列的最大特點是速度和精度，各通道均獨立同步及擁有兩片數字信號處理器晶元，當一晶元執行全部同步與取樣運算時，另一晶元則為已取樣的電流與電壓信號以真實18位解析度進行速傳立葉變換，電流與電壓具分離但完全同步的a d波形捕捉部份
  11. It first introduces the mpeg - 2 standard and the grammar structure of the ts. then it describes the principle of synchronization and multiplexing in digital communication. the synchronization comprises the carrier synchronization, bit synchronization, group synchronization and network synchronization while the multiplexing includes bit multiplexing, word multiplexing and frame multiplexing

    本文首先介紹了mpeg _ 2標準及其mpeg _ 2傳輸流語法結構，接著闡述了數字通信中的同步和復接理論，同步包括載波同步、位同步、群同步和網同步，復接包括按位復接、按字復接、按幀復接。
  12. According to the gjb 2077 - 94 and the requirement of automatic radio of haige communication co., a new way of bit synchronization is put forward. this article discusses the design of 8 - fsk modulating and demodulating, signal detection, and fec encoding, based on the technique of bit synchronization. ale module is optimized and mended in its application, because it is a module of automatic radio of the company

    本文根據gjb2077 - 94短波自適應通信系統自動線路建立規程和海格通信公司短波自適應電臺對ale模塊的具體需求，採用了一種新的位同步方法：能量跟蹤法，並在此基礎上提出了8fsk調制解調，信號檢測，前向糾錯編碼的具體實現方法。
  13. The line code is very efficient for bit synchronization in the communication systems and it is useful to choose the appropriate line code. the dissertation introduces the advantages of the manchester code, then studies the way to realize the encoding and decoding of the manchester code, and introduces the process of the joint - debugging on the whole system. the contents of this dissertation are as follows : 1

    本文首先討論了線路編碼與實現通信中位同步的關系，以此為出發點，討論了曼徹斯特碼作為一種線路碼于其他碼型的相對優勢，而後研究了編解碼器實現方案中的幾種待選方案，並對幾種方案做了對比論述后，設計了合適的方案，接著詳細研究了曼徹斯特碼編解碼器的硬體實現並進行了模擬。
  14. There are different ways to make the bit synchronization, for example : the technique of the pilot frequency, the technique of some change about the baseband signal

    為了保證在同步傳輸系統中的位同步，有導頻及對基帶信號信號直接變換的方式，直接變換的方式中，使用線路編碼是比較常見的。
  15. Frequency - domain equalization. at the same time discusses some key problems in ofdm : high ratio of peak - to - average power of output signals, problem of synchronization, channel estimation, adaptive bit, power and subcarrier allocation. emphasize on channel estimation, and present a new algorithm which can filtering more interpolation errors and noise. for the sake of improve the performance of resist narrowband noise and make efficient use of the spectrum apply malvar wavelet division

    同時就ofdm系統中的一些關鍵問題如峰值平均功率比（ papr ）太高，同步問題，通道估計，通道、比特與功率必須動態分配進行了研究，著重研究了通道估計問題並提出一種改進的方法，能濾除更多的噪聲分量和插值誤差，提高系統的性能；為了提高抗窄帶噪聲的性能和提高通道利用率，用malvar小波變換實現了不等帶寬分配。
  16. Both signals, synchronization and watermark, are embedded in the bit stream. a drift compensator is used to eliminate the distortion due to ac / dc prediction in i - vops and motion compensation in p - vops and b - vops, to maintain robustness of the watermark and the quality of the video, and resist format conversion attack

    採用漂移補償器來消除由於i - vop中ac dc系數預測和p - vop 、 b - vop運動補償編碼帶來的干擾和視覺降質，使水印有較好的魯棒性，抵抗格式轉換攻擊，並保證視覺質量。
  17. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  18. Thereby, the choice of external timing source brought by the changing from the el to qel has been resolved. in the related chapters, the paper will explain the arithmetic of synchronization of bit, frame and multiframe in the pm4354 hardware and describe the software arithmetic and hardware sketch map of net synchronization

    本文在相關的章節中將詳細地給出pm4354硬體上完成位同步、幀同步和復幀同步的實現的演算法，並給出qe1在實現網同步過程中的軟體演算法和硬體電路示意圖以及在項目開發過程中，測試以上各種同步技術是否可行的技術方案。
  19. With the current condition, the paper raises the point of synchronization in the qe1 ' s development, including the synchronization of bit, frame, multiframe and network and analyses the performance frame synchronization system based on the theory of probability and finally explains the realization of the technology of synchronization. the hardware circuit diagram of qe1 and some software flow chart have been offered in the paper

    在針對qe1中繼板卡系統實際的開發情況后，本文分析了該系統所涉及的同步問題（包括位同步、幀同步、復幀同步和網同步） ，在概率論的基礎上分析了qe1系統的幀同步系統的性能，並研究了各種同步技術在qe1中的實現。
  20. Recently, advances in postprocessing mechanisms have been studied to improve lip synchronization of head - and - shoulder video coding at a very low bit rate by using the knowledge of decoded audio in order to correct the positions of the lips of the speaker [ 3. 36 ], figure 3. 2 shows an example of the block diagram of such a postprocessing operation

    最近，對改善在很低比特率時頭肩像視頻編碼的唇同步問題的后處理機制的研究已經取得進展，這種機制運用解碼音頻的知識校正講話者的唇位，圖3 . 2顯示了一例這類后處理過程的框圖。
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