synopsys 中文意思是什麼
synopsys
解釋
辛諾普西斯軟體公司-
The flow of post - sim with synopsys nanosim amp; star - rcxt
的晶體管級后模擬流程 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
We use different commercial eda tools in order to achieve better implementation in different design phase, which include silicon ensemble of cadence, design compiler and design primer of synopsys and so on
在設計的不同階段使用了不同的主流eda工具進行輔助設計和驗證，包括synopsys公司的邏輯綜合工具designcompiler 、靜態時序分析工具designprimer和cadence公司的自動布局布線工具siliconensemble等。 -
3 ) design switch system using eda based on the result of a11alysis. because the function of switch system is very complicated, some modules are designed by schematics directly, most modules are designed by verilog hdl using eda technology, synthesized by the synopsys software. at last a high speed atm switch system is designed, including voq as input buffer strategy dpa cell scheduling algorithm and crossbar switch fabric
在前面分析的基礎上根據目前的條件，對一個空分交換系統各模塊進行前端設計和模擬，由於交換系統的功能復雜，我們一部分將採用直接畫原理圖的方法進行設計，大部分將採用集成電路設計自動化的方法進行設計，即採用硬體設計語言verilog ? hdl進行設計，用synopsys軟體對設計進行綜合，生成線路圖，然後作門級電路模擬。 -
The test bench program is a virtual pci system, which comprise the microblaze model established from xilinx edk and also the pci / pci - x model from synopsys company. function level or gate level simulation can be done on this test bench
測試平臺中，利用xilinxedk生成的microbalze處理器模擬模型，以及synopsyspci / pci - xflexmodels模型組建了一個虛擬的pci系統，可進行門級和行為級的模擬。 -
2. timing setup : load sdc ( synopsys design constraint ) file. define timing analysis options
2 .在時序設置階段，加入了時序約束，使整個設計在時序啟動下完成。 -
Synopsys ' s vera is one of the most modern languages designed specially for making testbenches
其中， synopsys公司的vera語言是專用於設計測試平臺的現代語言之一。 -
After a brief description of asic design flow adopted by pci target secure chip, the thesis make great emphasis on various methods and skills used in physical design and verification with apollo ii from synopsys
物理級設計：在對pci安全晶元所採用的的asic設計流程簡單介紹后，文章重點論述了基於apollo的物理設計和驗證方法和技巧。 -
After evaluating synopsys ' s formality, the paper construes the flow and practical experiences in video post - process chip, and comes to the conclusion that static verification really works
在簡單評價了synopsys公司的商用軟體formality之後，重點分析了在視頻后處理晶元項目中formality的應用流程和實際工作經驗，證明形式驗證的重要作用。 -
At last, we compile the design with synopsys design compiler in 0. 25wn cmos technology. the synthesis information about area, power and time shows that this method has the advantage of fitting special architecture into algorithms easily
最後用0 . 25 mcmos工藝在eda工具上實現，綜合結果表明：基於ip核的軟硬體協同設計方法，具有具體結構對演算法的適應性好、設計周期短、系統易於優化等特點。 -
Then, a new design automation methodology is put forward which uses uml for specification, systmec for simulation and synopsys tools ( cocentric systemc compiler ) for hardware synthesis. the main feature of this methodology is its high possibility of implementation
提出了一個基於uml系統描述的， systemc模擬驗證的，利用cocentricsystemccomplier進行硬體綜合的自動化設計方案，這個方案最大特點是可實現性強。 -
Except for design methodology and technique, some comprehensive experiments are performed. these experiments use some eda tools, including functional simulation with cadence ' s verilog xl, logic synthesis with synopsys ' s design compiler
本文除了介紹的設計方法和設計技巧，還做了一些有益的實驗，使用到許多流行的eda工具，如cadence公司的verilog - xl 、 siliconensemble ， synopsys公司的designcompiler 、 physicalcompiler等。 -
Then, we use software hspice of synopsys to realize the inductor macromodel, and the circuit system responding to hysteresis mathematic model can be designed well, meantime, the method of building the macromodel lay technical foundation for other circuits design and that simulation results approach to real behaveior
然後，利用synopsys公司的電路模擬軟體hspice實現磁芯電感宏觀模型，完成了與整個磁滯數學模型相對應的電路系統的設計，為其它電路系統的設計，以及模擬結果更接近實際工作情況奠定了良好的技術基礎。 -
Cadence and synopsys eda tools is applied as design tools of this design, and having front - end simulation with verilog _ xl of cadence, having back end application simulation with hspice of avanti. after design finished we had twice mpw order sequence, and the test result of the sample conform to the request of design
本次設計是在cadence和synopsys等eda設計工具上完成的，並進行了前端的verilog _ xl功能模擬驗證和後端hspice的器件模擬，在完成整個設計流程后先後進行了兩次mpw投片，其樣片的測試結果達到了設計要求。
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