test bus 中文意思是什麼

test bus 解釋
測試用匯流排
  • test : n 1 檢驗，檢查；考查；測驗；考試；考驗。2 檢驗用品；試金石；【化學】試藥；（判斷的）標準。3 【化...
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  1. Endurance test for truck and bus tyres - drum method

    載重汽車輪胎耐久性試驗方法轉鼓法
  2. 1. whole signals of pci bus test socket converter extender maybe

    1 .所有的轉換卡信號
  3. Application of vxi bus in field of the srm ground test

    總線系統及在固體發動機地面試驗中的應用
  4. Design of automatic test system for power supply based on gpib bus

    機載雷達自動測試系統設計
  5. It is implemented by dll programming with psasp / upi. the 14 - bus ieee test system has shown validity of the model and feasibility of proposed algorithm, which quantifies the role of facts devices

    Ieee14節點測試系統的計算結果表明了模型的正確性和演算法的有效性，並量化了facts元件對ttc的影響
  6. Do you design or test pci bus add - on card now

    您正在研發，測試pci bus的介面卡嗎
  7. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  8. A very long burst read and combined write scheme on pci bus is proposed to achieve maximized pci performance test results show that end - to - end bandwidth is about 175mb s in single - net system and over 300mb s in double - net system the performance of hvia - net is endsville compared with current high performance commodity network in the world hvia - net has successfully been used in galaxy super server

    提出了一種超長讀突發和寫報文合併技術，最大限度地利用pci總線的性能。實際系統測試結果表明，單網點-點帶寬達到175mb / s以上，雙網點-點帶寬達到300mb / s以上。與目前國際上的高性能商用網路相比， hvia - net的性能是領先的。
  9. But this is premised on the perfect communication between field machines and remote monitor. thus a polling way was defined to control the media access to the bus built with rs - 485 interface. within the long period of test run, the whole system was proved to be effective

    項目中利用rs - 485介面組成總線網，採用自定義的輪詢方式控制總線的介質訪問，經過反復調試，成功實現了多個從機與單臺監控主機之間同時進行的實時通信。
  10. Part two : design the schematic of the intelligent communication card ; to apply protel99 software to design sch and pcb charts, then send them to the factory ; to debug on the hardware and test on can bus chip ; to program assemble language control and can bus communication software of the intelligent communication card and debug on the super ice16 simulator ; to utilize the super ice 16 simulator to debug the control programs of the communication card online ; link to control card and debug the can bus communication program online ; to debug the system on eprom

    第二部分：設計can總線智能通信卡的硬體電路，應用protel99設計軟體繪制原理圖及印刷電路板圖，並送廠製作板卡電路板:智能通信卡硬體製作和can總線晶元調試;編寫通信卡控制及can總線通信匯編語言程序並編譯;在superice16模擬器上在線模擬調試控製程序;連接系統控制卡，模擬調試can總線通信程序;程序燒入eprom晶元，進行系統eprom模擬調試;介面系統驅動程序及測試軟體調試。
  11. Strength test method for truck and bus tyres

    載重汽車輪胎強度試驗放方法
  12. 3. using the vpp code in labview and vxi bus, a softwar is programmed for the driving signals generating and the response signals sampling. the software can process the data to appropriate the exciting force, control the whole test and display the response curves

    3 .在labview環境下，調用vpp節點驅動vxi總線來實現多通道正弦激勵信號的生成、響應信號的採集與處理、不同激振力之間的相位協調以及測試結果的動態顯示、儲存。
  13. This paper discusses some research result related hev energies management system on basis of the development of hybrid electric bus - wg6120hd. the basic structure of hev energies management system is developed. the energies management system includes battery management sub - system ( bms ), engine management sub - system ( ems ), vehicle information sub - system ( vis ), energy regenerated management sub - system ( erms ), generator / electromotor management sub - system ( g / ems ), do some theory researches with test results

    本文結合混合動力電動大客車wg6120hd的開發經歷對混合動力電動汽車多能源控制系統探討了如下研究工作：建立了混合動力電動汽車多能源控制系統的基本結構，開發出了蓄電池管理子系統、發動機管理子系統、駕駛員信息子系統、能量再生控制子系統、發電機電動機管理子系統等組成部分，結合採集的有關數據對各個子系統從理論方面進行了深入探討，為以後進一步的研發工作打下了基礎、積累了經驗。
  14. As the requirements of its function, a bus control interface board has already been designed. also the paper have provided the scenarios demonstration for the bus control interface board ( bcib ), the design for the protocol of communication, the hardware for bcib, the software for bcib, and the software for the processor ' s communication. while the analysis for the capability of real - time and the calibration and test for subsystem have been also finished. during the design, the system advanced ability, reliability, resources availability and the cost - efficency ratio are considered. the issus such as system integrated control, mutual exclusion of the shared storages, generation of handshaking signal and system self - test were resolved

    本論文主要對航空自衛系統的綜合化方式進行了深入研究，並按其功能等方面要求，對航空自衛系統綜合化總線通信模塊進行了設計，主要完成了總線通信模塊方案論證、通訊協議設計、總線通信模塊硬體設計、總線通信模塊（ bcib ）軟體設計、處理機通信軟體設計、實時性分析、系統調試、試驗等項工作，在設計過程中，綜合考慮了系統先進性、資源利用率、費效比及可靠性等因素；重點解決了系統綜合控制方式、共享存儲器互斥、握手信號產生及系統自檢測等問題。
  15. The proposed methodology is tested on the ieee - 5 bus system. the test results verified the validity of the proposed concept and method

    通過對ieee - 5節點進行無功容量費用和無功電量電價的模擬計算，結果表明本文觀點和方法是可行的。
  16. Mixed signal test bus

    混合信號試驗總線
  17. In this paper, ieee1149. 4 std mixed - signal test bus and its characteristic are studied. according to the structure defined in this standard, test methods of mixed - signal circuits are studied. the mixed - signal boundary - scan test system, which is complianted to ieee1149. 4 std, is designed

    本文深入研究了ieee1149 . 4混合信號測試總線及其特點，並根據邊界掃描標準定義的測試結構對混合信號電路的測試方法進行研究，設計出符合ieee1149 . 4標準的混合信號邊界掃描測試系統。
  18. Standard for a mixed - signal test bus

    復合信號試驗總線標準
  19. The main contents are as follows : the structure of mixed - signal circuit which newly - defined in ieee1149. 4 std is analyzed in detail, especially anolog boundary module and test bus interface circuit. on the basis of mixed - signal boundary scan technology, a scheme of mixed - signal boundary - scan test system is presented and the hardwares are implemented, including the controller and display unit

    主要研究的內容以及所作的工作如下:詳細分析了ieee1149 . 4標準中針對混合信號電路測試新增的結構，即模擬邊界模塊及測試介面電路。基於混合信號邊界掃描技術標準，提出混合信號邊界掃描控制器的設計方案並實現了其硬體設計，包括邊界掃描控制模塊、顯示驅動模塊等。
  20. The development and capability comparing for the test bus

    測試總線的發展及性能比較
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