timing clock 中文意思是什麼
timing clock
解釋
定時機構-
Examples of gearboxes can be found on the transmission in a car, the timing mechanism in a grandfather clock, and the paper - feed of your printer
變速箱的示例可以在汽車的傳動裝置、落地大座鐘的定時機制和印表機的送紙裝置中找到。 -
Inside the instrument has many kinds of scaling conversation formula which can carry out chosen scale conversation such as convert into length etc. digital clock timer wide use to clocking, timing in every industry field. it is operate brief, clocking accuracy, timing alarm, and with outer connected start stop, clear function
本表含有前述智能流量積算控制儀的全部功能，增加了獨特的防盜措施，提高了系統的安全性，即使在斷電的情況下，亦可有效地防止盜用，保證了用戶的準確計量使用，且操作簡便，可靠性高。 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation
並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。 -
Circadian rhythms can be affected to some degree by almost any kind of external time cue, such as the beeping of your alarm clock, the clatter of a garbage truck, or the timing of your meals
生物鐘節律在一定程度上可以受任何外界時間線索影響，如鬧鐘的聲音清潔車的聲音及進餐的定時等。 -
Finally the timing problems in high - speed circuit design were analyzed and the conditions of timing design in source synchronous clock system were derived
最後分析了高速電路設計中時序問題，給出了源同步時鐘系統中時序設計應該滿足的條件。 -
Based on the basic principle of wavelet analysis, multi - resolution analysis of signal in atomic clock is made. the coefficients of wavelet transform for synthesis atomic time, which are weighed and averaged at different wavelet scales, are obtained. then according to reconstruction theorem, multi - resolution synthesis time scale can be reconstructed. since the signal of atomic clock has been analysed by multi - resolution, we can use wavelet variance at different scales to weight and average the coefficients. thus either the difference in stability of different clock or the varying characteristic of the same clock at the different scale are all considered. finaly, this method is checked by the measured data from national timing serve center of shaanxi astronomy observatory. it confirmed that this technique, which is simple and practicable, is a new method of multi - resolution. from this method, the common characteristic of different clocks can be extracted. the stability of multi - resolution synthesis atomic time scale is obviously superior to that of other methods
本文根據小波分析的基本原理，對原子鐘信號進行多解析度分解，將分解后的小波變換系數進行加權平均，得到不同小波尺度綜合原子時的加權平均小波變換系數，然後由小波變換的重構條件，反演綜合時間尺度.由於對原子鐘信號進行了小波分解，利用不同尺度的小波變換系數的小波方差進行加權平均，這樣既考慮不同原子鐘在穩定性方面的差異，又顧及同一臺原子鐘在不同小波尺度的變化特性.最後根據陜西天文臺國家授時中心的實測數據對這種方法進行了檢驗.表明這是一種全新的多解析度綜合方法，這種方法比較簡單而切實可行，它能提取各個原子鐘的共同特性，多解析度綜合時間尺度的平穩性明顯優于其他方法 -
Node clock set of digital synchronization network and its timing feature
數字同步網節點時鐘系列及其定時特性 -
However in soc or high performance cpu an in - chip high quality clock is required to guarantee the timing of all chips
而soc或者高端的cpu一般都採用同步的數字電路設計，時鐘是整個晶元時序的保證。 -
Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment
Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。 -
Based on the coherent reception theory of radio signals and the theory of digital signal processing, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on ofdm signals are exploited. a series of amendments and new algorithms is derived from the in being algorithms of guard interval based symbol timing and frequency offset estimation, frequency - domain frequency offset, sampling offset, and symbol timing offset estimation
以無線信號的相干接收和數字信號處理理論為基礎，就載波頻偏、采樣鐘偏差和符號定時偏差對ofdm信號的影響進行了分析，對基於保護間隔的符號定時與載波頻偏估計演算法和多種現有頻偏、采樣鐘與符號定時偏差的頻域估計演算法進行了研究，提出了一系列改進措施與新演算法。 -
After power switch opening, the clock displayer display asynchronous timing information, so synchronous indicating lamp glimmer, when equipment receiving above four effective satellite information and getting synchronous, which synchronous indicating lamp blank off
電源開關打開后，時鐘顯示器顯示未同步的時間信息，同步指示燈閃爍，裝置接受到四顆以上的有效衛星信息，並取得同步后，則同步指示燈熄滅。 -
《 guiding clinical nursing with the theory of “ biological clock ” 》 abstract the importance of timing nursing was studied according to regular change of body rhythm ( biological clock ). the closed relationship between illness observation, clinical use of medicament and timing nursing was discussed
摘要從人體節律的規律性變化（生物鐘） ，探討了實施時間護理的重要性，並詳細闡述了病情觀察、臨床用藥與實施時間護理的密切關系。 -
Irig - b clock code generator in gps timing
時間碼產生器設計 -
Our basic idea is to make use of the permissible clock skew to enhance the timing reliability of a circuit
我們的基本想法，是利用可允許的時序差異值來提高電路的時序可靠度。
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