timing design 中文意思是什麼
timing design
解釋
時制設計-
This paper introduces common background knowledge of intersection, mainly describes traffic control design principle, such as signal timing and lane channelization. it also summarizes the same point between signal timing and lane channelization in nature and illustrates that it is optimal cycle length and signal phase that is the critical part of signal timing
=本文介紹了交叉口的一般背景知識，重點闡述了平面信號交叉口的交通控制的設置原理，包括信號配時原理和路口渠化原理，概括了信號配時和路口渠化原理的本質相同點。 -
The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。 -
Based on the field exploration and long - term underground observation, this paper reveals the zoning of structure and the timing of mechanical strength for dilative soil, and puts forward the experiment method to obtain values by zoning in the design of dilative soil slope
通過野外勘探及地下長期觀測，揭示了膨脹土的結構分帶性和力學強度的時效性，提出了膨脹土邊坡設計中分帶取值和試驗方法。 -
In addition square design 12 the heavenly stems the twelve earthly branches column in the sun, ancient the heavenly stems for timing tool the twelve earthly branches, implied meaning to represent time, i hope, can with theme of sand at the i, echo each other, the building in the middle of the sun square is set as the round, hope it has by the look of on the plane figure been a stereoscopic round, and cover the ground and adopt the magnificent style that publicize, to reflect the enthusiasm of day is publicized, in addition the section of dim light of night represented by moonlight restaurant, i plan to have light more, can let people can fully experience the soft light makes the dim light of night pleasantly
此外在太陽廣場設計了12根天干地支柱，古代天干地支為計時工具，代表時間的寓意，我希望能和我時之砂的主題，相互呼應，太陽廣場中間的建築物設為圓形，希望從平面圖上看來是個立體的圓，而鋪地採用華麗張揚的風格，來體現日的熱情張揚，此外以月光餐廳為代表的夜色段，我打算多設燈光，能讓人能充分感受到柔和燈光下夜色迷人。 -
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。 -
On the operating design of raas, the paper focused on the change of task _ struct, the design of kernel process kaasd, the timing of raas, the configuration and initialization of raas in the end, the paper evaluate the raas from the aim of system design, the integration with the other secure components of secure os, provide some problems unsolved, such as the expanding to network monitor, the new technology of ids
對于實時審計分析系統的整體運行設計，從操作系統原有數據結構task _ struct的改變，內核進程kaasd的設計， raas的定時和系統的配置和初始化這幾個方面逐個進行敘述。在本文的最後，從raas的達到的目的，與原有安全功能的有效合成等方面對該系統作了一個評價，同時提出幾個需要進一步思考的問題，如對網路的擴展，對入侵檢測新技術的引入等 -
Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design
在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。 -
Design about frequency conversion timing system of hydraulic support test pump station
液壓支柱試驗泵站變頻調速系統設計 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
The whole circuit ' s timing generation and synchronization was realized with cpld. as the channel of data transmitting, pof can isolate high voltage part and low voltage part efficiently. at the same time, a single chip processor was used to design a digital meter for the fiber current transducer
系統採用cpld實現整個工作電路的時序發生和同步協調，利用光纖實現高壓部分和低壓部分的完全電氣隔離和實現信號傳輸，採用單片機技術實現混合式光纖電流互感器專用數字顯示儀表的設計。 -
According to the characteristics of the overhead camshaft valve train, the author thoroughly analyzed the kinematics and dynamics concerned in the design of valve train cam profile. the results illuminate the influence of valve timing, ample factor as well as the contact stress between cam and tappet on the design of cam profile
根據頂置凸輪軸式配氣機構的特點，文章深入分析了在配氣凸輪型線設計中必須涉及的運動學及動力學問題，說明了配氣定時、豐滿系數及凸輪與挺柱間接觸應力對凸輪型線設計的影響。 -
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
Following describing the system ' s organisation, we discuss the design and implementation of the system in detail including data paths, alu. to design the control paths, we start with the analysis of mcs51 instruction set, and then discuss the instruction execution procedure instruction and operation, and schedule of instruction timing
Risc51ipcore控制通路的重點是兼容mcs51單片機指令系統的設計與實現，本論文從mcs51指令系統的分析入手，詳細討論了指令的執行流程、內部指令和操作的設置、指令的時序安排的設計與實現。 -
In this thesis, the research on short - range high accuracy range finding system, which is inexpensive and compact, is done. to design the laser transmitter and the timing circuit is the main task
本文旨在針對成本低、體積小的高精度短程激光測距系統開展研究工作，主要任務是設計與實現脈沖激光測距系統中激光發射器電路和計時電路。 -
Finally the timing problems in high - speed circuit design were analyzed and the conditions of timing design in source synchronous clock system were derived
最後分析了高速電路設計中時序問題，給出了源同步時鐘系統中時序設計應該滿足的條件。 -
This article is focused on the course of designing the apparatus of micro - friction. in this article, the paper describes three parts, the design mehods and principles of forcing sensor and turning equipment, the choice of electromotor and hardware of timing design
本文詳細論述了微小摩擦力測試儀的總體設計過程，主要包括測力傳感器和轉動裝置的具體設計原理和方法及電機的選用和調速硬體設計。 -
The heart rule of synchronization timing design was proposed. the debugging theory of software for hardware was summarized
提出同步時序設計的「心跳法則」 ，總結了以軟描硬的調試理論。 -
The thesis expounds the cell design and timing design of the fpga circuit in main controlling and baseband signal processing module, and develops the hardware of it, and programs part of the software
文中詳細闡述了主控與基帶處理單元中fpga模塊設計與時序設計，研製了主控與基帶信息處理單元硬體，編寫了部分調試軟體。 -
The thesis then introduces top - to - bottom schemes, which discuss the functional design of hdtv test pattern signal generator according to the tasks and platform of the system, and develops the function of subsystems. the thesis analyses the theory and mathematic model of hdtv test signal, and studies the signal generating scheme called single - fpga and multi - prom, and describes in detail its key modules such as configuration connecting, prom routing, control and switch timing design and so on. the single - fpga and multi - prom scheme increases the number of prom to reduce the degree of fpga demanded, thus
論文分析了hdtv測試信號的原理及數理模型，提出了一種以單晶元多配置為特色的信號生成方案，並對該方案的配置連接、晶元選路、控制切換時序設計等關鍵模塊進行了詳細敘述，該方案以增加配置晶元數量來降低對主晶元要求，不但降低了產品成本，還使各測試信號的代碼編寫和產生相對獨立，有利於合理使用晶元資源，實現多種復雜的hdtv測試信號，縮短開發周期。 -
Signal timing design
信號時序設計
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