two-level circuit 中文意思是什麼
two-level circuit
解釋
二級電路-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox
本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。 -
In the experimental system apd transferred laser pulse to weak electrical current. after two - level amplification we got a voltage pulse that had a enough amplitude to be applied, the timing point was discriminated by the constant - fraction timing discriminator circuit. timing circuits transferred the pulse flight time to digital signal accurately
實驗系統採用apd作為光電傳感器，將激光脈沖信號轉變為微弱電流脈沖，經過兩級放大后，信號變為幅度較大的電壓脈沖，經過時點鑒別電路分別確定計時起點和終點后，由計時電路來精確測量兩個時間點之間的時間間隔。 -
Capacitance between any two terminals in the installation should no more than 1. 06. 3. insulation level of installation : for rated voltage of 6kv installation, it can endure 23kv rms for 1 min between the phrase to phrase or phrase to earth of main circuit ; for rated voltage of 10kv installation, it can endure 30kv rms for 1 min between the phrase to phrase or phrase to earth of main circuit ; it can be endure 2kv rms for 1 min between auxiliary circuits of installation
3 .裝置的絕緣水平： 6kv額定電壓的成套裝置，其主電路相間及相與地之間，工頻耐受電壓方均根值23kv ， 1min 10kv額定電壓的成套裝置，其主電路相間以及相與地之間，工頻耐受電壓方均根值30kv ， 1min成套裝置輔助電路工頻耐受電壓方均根值2kv ， 1min 。 -
The percentage of time that a circuit or device with two operational states is in the higher level or more active state
一個有兩個工作狀態的電路或設備處于高電平狀態或經常活動狀態的時間百分比。 -
The core of epiipc is the 51 series microcontrollers, which automatic detect the error signal of the circuit, like short circuit, overload, high voltage, low voltage, current leakage etc. meanwhile it monitors and tests the insulation level of high voltage cable, with convenience two variable key setting and full chinese version lcd display features
本次研製的保護器以高檔51系列單片機為核心，能自動判斷線路中出現的短路、過載、過壓、欠壓、漏電等故障，並對高壓電纜的絕緣水平進行實時監測，有方便的兩鍵參數設定和全中文液晶顯示功能。 -
The double dsp devices are used to sample data and process the signals in the power disturbance monitoring and analyzing part. the power quality conditioner integrates active power compensation with passive power compensation, and improving power quality with improving power factor. the conditioner circuit consists of tri - level pwm converters, in which there are two active power filters ( apf ) that is a shunt apf and a series apf
電能質量監測分析系統採用雙dsp實現系統的采樣、信號處理，完成電能質量全程監測與分析；電能質量調節系統則採用有源與無源、改善電能質量與改善功率因數相結合的策略，有源部分以三電平pwm為主電路，由並聯和串聯apf （ activepowerfilter ）相結合、共用直流電源，構成其主體框架，並以無源調節配合有源調節來降低系統的綜合造價，力圖將電能質量調節技術在10kv配電系統中得到實用與推廣。 -
Structuring three - level model on basis of two - level model. published before. the circuit model is simulated and some results are gotten by taking account into the same parameters. mqw - ld circuit model designed by grossi is adopted to be illustrated by some solo subcircuits
在已發表的二層電路模型基礎上提出了三層模型，在所依據的參數基本相同的情況下，對模型進行模擬，並對所獲的結果進行比較討論。 -
Because the signal which serial interface output of mcu is ttl logic level, it is essential to transform ttl electrical level to rs - 232 electrical level when the mcu is communicated with pc. in this paper the universal rs232 / 485 electrical level converting circuit board is designed. it can realize data transmission by the two communication level manner
因為單片機的串列輸出介面輸出的電信號是ttl電平，這樣在和上位機通信時需要通過轉換電路對其電平進行轉換，所以在本課題中設計了通用的rs - 232 485電平轉換電路板，可以實現兩種不同電平的數據傳輸，通過最後的實驗驗證，該電路板能實現所要求的功能，傳輸信號可靠準確。 -
With application and circuit gateways, all packets are addressed to a user - level application on a gateway that relays packets between two points
用應用軟體與線路入口時，所有的包都按地址送給入口上的用戶級應用程序，入口在兩點間轉送這些包。
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