video chip 中文意思是什麼

video chip 解釋
視頻微型磁片
  • video : n. 電視；視頻；影像。adj. 電視（用）的，視頻的，錄像的。
  • chip : n 1 碎片，削片，薄片；碎屑；薄木片；無價值的東西。2 （陶器等的）缺損（處）。3 （賭博用）籌碼；〈p...
  1. This paper refers to several creation in compatibility with large volume of fed display and conversion of different video signal. it firstly used special central chip al300, designed correlative circuits, successfully developed vga full - color fed console system, compatible with resolution 1280 1024, achieved functions such as multi - video signal conversion and interleaving, met vga ’ s resolution of fed. it firstly designed and fabricated vga interface and separated video interface - - s - video, converting several video signals to 24 bits full - colored digital image signal in fed driving system, achieved separation of luminance signal and chromatism signal, enhanced the bandwidth of luminance signal

    首次採用平板顯示專用控制晶元al300 ，設計並製作了相關配套電路，支持的最高解析度是1280 1024 ，實現解隔行和多種視頻格式轉換的功能，滿足了fed顯示屏對vga解析度的要求。首次在基於fpga的vga級彩色fed控制系統中設計並製作了vga介面和分離電視信號s - video介面，可以將多種視頻信號變換為fed驅動系統可用的24位彩色數字圖像信號，實現亮度信號和色差信號的分離，提高了亮度信號的帶寬。
  2. The function of video card memory played down apparently on the display card is similar to memory in the computer ; its function is to preserve the data dealt with to display chip - picture element temporarily

    顯卡上的顯存所發揮的作用與電腦中的內存差不多，它的作用是暫時存放顯示晶元所處理的數據?像素。
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. Blackfin533 is the new multimedia chip of ad incorporation. the study on h. 264 standard and its implementation on blackfin533 is important to the application of video techniques on embedded system

    Ad公司推出的blackfin系列dsp晶元是針對視頻技術而開發的專門晶元，因此，研究h . 264視頻標準並研究其在blackfindsp上的應用對視頻技術在嵌入式領域的應用研究有重大意義。
  5. The thesis discusses on how to research and then design the led video panel system, which is a typical product of computer digital video system, by using the pld chip as the main control logic

    本論文討論用pld晶元作為主要控制邏輯來設計計算機數字視頻系統的一個典型應用型產品? ? led視頻電子顯示屏系統的研製方法。
  6. The function of video frequency gathering board is to reveal the compound television signal from the computer to carry on a / d transforms, rgb separation processing and so on, output 24bits rgb signals and the synchronized signals. these functions were finished by video frequency decoding chip saa7111 made by philip corporation

    視頻採集板的功能是利用philip公司的視頻解碼晶元saa7111 ，對計算機顯卡輸出的復合電視信號進行a / d轉換， rgb分離等處理，輸出24位rgb信號和同步信號。
  7. A h. 263 real - time video coding system based on dsp chip is then designed which follows the develop flow of a dsp system

    然後按照dsp系統的開發流程，設計開發了一個基於dsp晶元的h . 263實時視頻壓縮編解碼系統。
  8. First an analog video signal is decoded by saa7 11 a to form a digital video signal complying with ccir6o1 which then is compressed by an special chip ibms42o, at last, the video es is packed with audio es to form ts by computer

    具體來說，是把模擬視頻源解碼成符合ccir601規范要求的數字視頻源，經專用的mpeg2編碼晶元壓縮形成視頻es流送入計算機，與一路音頻es流打包復用后形成一路ts流。
  9. Among many methods that realize video coding, the method based on dsp chip also bears remarkable advantage besides pure software method which used widely

    在諸多視頻編碼實現方法中，除了已廣泛應用的純軟體方法外，基於dsp晶元的方法具有顯著的優勢。
  10. And it has been integrated in a prototype chip which is fabricated with tsmc 0. 18 - um cmos technology, and the experimental results show that this architecture can achieve the real time avs - p2 decoding for the hdtv 1080i 1920 1088 4 : 2 : 0 60field s video. the efficient design can work at the frequency of 148. 5mhz and the total gate count is about 225k

    為支持直接模式預測，該模塊通過一個fifo來實現p圖像下mv緩存和b圖像下mv預取的功能，以突發方式來進行訪存操作，從而避免了頻繁而瑣碎的訪存請求，使外存控制器能夠更好地為其他訪存模塊服務。
  11. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  12. Application of the fir filter in single - chip for video format conversion

    有限長脈沖響應濾波器在視頻格式轉換晶元中的應用
  13. Method study of video compression based on adv601 chip

    601實現視頻壓縮的方法研究
  14. Digital - video encode - decode chip, one of the basic components of digital - video devices, is still relying on import products

    數字視頻解碼晶元是數字電視等視聽設備的核心器件，目前絕大多數仍依賴國外進口。
  15. H. 323 is the standard about multimedia communication released by itu - t. tm1300 including a very powerful, general - purpose vliw processor core ( the dspcpu ) that coordinates all on - chip activities is a media processor for high - performance multimedia applications that deal with high - quality video and audio. the dspcpu implements a 32 - bit linear address space and 128, fully general - purpose 32 - bit registers

    H . 323是itu ? t推出的用於ip分組網路的多媒體通信終端協議， trimediatm1300處理器晶元是philips公司推出的一種基於多媒體應用的具有vliw指令，含有128個通用寄存器， 32位的高性能處理器，它能夠通過編程實現通信協議，完成高質量的音頻、視頻處理和網路介面。
  16. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0

    本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
  17. Since the mpeg - 2 decoding chip is a soc, 32 - bits embedded risc cpu core is used to decode the ac3 and ts bit stream. the risc core is also used to manage the different task in the chip and the video processing unit is realized in asic modules

    論文設計的mpeg - 2系統集成解碼晶元是一個soc ，該soc採用32位嵌入式risccpu核virgo進行音頻ac3和ts流解碼的計算任務，並承擔soc的管理；視頻解碼採用asic實現。
  18. It ’ s a 16 / 32bits risc cpu based on arm920t ip core, which is highly integrated and powerful. this cpu has a lot of peripheral interfaces and i / o ports, which will facilitate our system design. the asic ime6400 is a system level chip which supports the multi - channel mepg4 video / audio compression. in our design, it ’ s served as an video compression oriented co - processor working under the control of s3c2410x. s3c2410x will do the job of importing the other vehicle traveling data such as analog and switch signals

    在筆者設計的系統中， ime6400作為專門進行數字視頻信號壓縮的協處理器，與s3c2410x協同工作，完成視頻信號的獲取，壓縮等工作;同時利用晶元的片內外設（如ad轉換器和i / o口） ，完成汽車行駛過程中開關量和模擬量的獲取和存儲，以滿足一個記錄儀的基本功能需求。
  19. Epp based verification scheme for video chip

    並口的視頻晶元驗證
  20. If you have multiple video cards, or a disabled onboard video chip plus a video card, desktop effects may not be able to configure / detect them correctly

    如果您有多塊顯卡或禁用了主板的集成顯卡，桌面效果也許不會正確地配置/檢測到它們。
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