介面電路晶元 的英文怎麼說

中文拼音 [jièmiàndiànlùjīngyuán]
介面電路晶元 英文
interface circuit chips
  • 面 : Ⅰ名詞1 （頭的前部; 臉） face 2 （物體的表面） surface; top 3 （外露的一層或正面） outside; the ri...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 介面 : joggle; nozzle; mouthpiece; [計算機] interface
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops

    為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。
  2. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  3. Nowadays, all functions of a calculator including calculating units, display driver, keyboard interface and so on, are integrated on one single chip

    現代計算器使用一塊集成電路晶元來完成各種運算、顯示驅動和鍵盤介面等完整功能，依賴的是高度集成的動態cmos邏輯和微碼設計技術。
  4. In order to make the sensitivity of 2 - demension accelerometer along the two main arbors almost identical, symmetric four - beam structure that embeds a double - sides interdigitated differential capacitive with puckered beam in two directions was used as sensitive component. in addition, the differential capacitive accelerometer fabricated by bulky silicon micromechanical technique has high sensitivity, wide measurement scope, less nonlinear error, and simple converting circuit. then, the structure parameters of the sensitive component were calculated and stimulated, which results in a set of the optimized structure design parameters, main fabrication procedure and several key fabrication technology

    為使二維振動傳感器在兩主軸方向的靈敏度大致相同，敏感元件採用高度對稱的四梁結構，其中每個軸向上均採用帶折疊梁的雙側叉指電容結構，採用體硅微機械工藝製作的高深寬比叉指電容式敏感元件，具有高靈敏度、寬量程、非線性誤差小、外圍電路簡單等優點;對設計的敏感元件結構參數進行了計算，並利用有限元法進行了模擬分析，根據模擬結果得出了優化參數;在確定敏感結構的基礎上，研究了敏感元件採用體硅微機械加工工藝製作的工藝流程和關鍵工藝技術;對敏感晶元內部的c - v介面電路進行了原理設計與分析，利用差動測量技術得到由振動引起的微小電容變化量，經c - v介面電路進行相位調制處理，然後通過解調輸出與加速度成正比的電壓信號。
  5. The hardware of the system is made up of p89c61x2ba as main processor, usbn9604 as usb interface, grating signal - processing circuit, xc95108 as signal subdivision, sensing, counter circuit and so on

    硬體部分以p89c61x2ba為控制核心，包括採用usbn9604介面晶元的usb介面電路，光柵尺輸出信號處理電路，以xc95108為主的信號細分、辨向和計數電路等。
  6. It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks

    在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。
  7. And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed

    本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。
  8. In the designed hardware, at89c51 single chip computer and many kinds of new type circuit chip ( including : special power measuring chip - cs5460a, ds1302 calendar / clock chip, sms0601 lcd, x5045 serial memory ) are used for design. the hardware circuit is simplified, the meter ' s anti - interference ability is enhanced and the precision of measurement is also advanced

    設計中以at89c51單片機為核心，採用多種新型集成電路晶元（包括電能計量專用晶元cs5460a 、 ds1302日歷時鐘晶元、 sms0601液晶顯示器、 x5045串列存儲器）進行介面設計，簡化了硬體電路，提高了電能表的抗干擾能力和測量精度。
  9. Introduces operation principle and interface circuit design of video input processor saa7111 and video output processor saa7185. 4

    介紹了可編程視頻輸入編碼晶元saa7111和可編程視頻解碼輸出晶元saa7185工作原理和介面電路設計。
  10. The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method

    該傳感器製作工藝簡單，靈敏度高，支撐梁採用u型，減小了刻蝕后的殘余應力，用玻璃作為襯底，減小了襯底和硅可動質量塊間的寄生電容，且把傳感器晶元和用ic裸片製作的介面電路集成在一起，提高了封裝密度，減小了傳感器系統的噪聲，為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。
  11. The paper designs a type of circuit which combines gps receiver with computer by means of the icl232 integration chip. it achieves deliver and receiver at the same time. it gives receiver program chart

    採用icl232單電源集成電路晶元設計gps接收機與微型計算機介面電路，可以同時實現發送和接收信號的電平轉換，並給出了接收的流程圖。
  12. The basic principle of natural gamma - ray log is stated, the developing background, developing ways and developing situation of natural gamma - ray tools are introduced. the researching task of the paper is presented through analyzing the using situation and questions exsisted in inner natural gamma - ray tools, the researching work is started from three aspects, they are logging tool development, reliability design and reliability assuring methods, and the data processing methods, in the course of logging tool development, instrument indexes are presented based on the compatible property of sookbps telemetry system and environmental property, the analog measuring chanel and the interface circuit which realizing the compatible performance are designed according to the instrument mdexes. the detecto * design. the plateau property testing of the detector and the analysis of it ' s affecting factors are stated, the measuring property of the tool is discused, a new type of single chip microcomputer is selected when designing the interface circuit, and the laboratory experiments has fulfiled conmunieating standard signals between the interface circuit, the universal interface unit of sookbps telemetry system and also 500kbps telemetry system

    本文首先概要介紹了石油測井的基本概念、方法、條件、最新進展、以及應採取的研發對策，論述了自然伽瑪測井的基本原理，介紹了自然伽瑪測井儀的發展背景、發展歷程和發展現狀，通過分析國內自然伽瑪測井儀的使用情況和存在的問題，提出了本文的研究任務。研製工作從測井儀研製、可靠性設計與可靠性保障技術、數據處理方法研究三個方面展開，在測井儀研製過程中，根據500kbps遙傳系統要求的配接性能和使用環境特徵，提出了主要儀器指標，並根據這些指標，設計了儀器模擬測量通道和實現這一配接性能的介面電路；論述了探測器的設計、坪特性影響因素分析及其測試，探討了儀器的測量性能；在設計介面電路時選用了新型單片機晶元，並與500kbps遙傳通用介面單元rtu 、 500kbpa遙傳系統實現了室內配接。
  13. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  14. The signal generator of sweep frequency is based on dds device ad9954, the signal measuring circuit is based on gain and phase detector ad8302, the real - time control and deal circuit is based on tms320vc5409, and the periphery interface circuit is based on at89s52. the system can generate sweep frequency signal with the frequency range from 100khz to 150mhz, and with the power range from - 45dbm to + 18dbm. it can measure the gain and phase of the network, display the measure data by liquid crystal displayed and print it by the printer

    該測試儀以dds晶元ad9954為核心構成掃頻信號源電路，以增益相位檢測器ad8302為核心構成檢測電路，以dsp晶元tms320vc5409為核心構成控制與運算電路，以及以at89s52為核心構成外圍介面電路。該測試儀能產生頻率范圍達100k ~ 100mhz ，功率范圍為- 45dbm ~ + 18dbm的掃頻信號，能對被測網路的頻率特性進行測量，並留有豐富的外圍介面，可以將測量數據繪圖通過lcd顯示或者由印表機列印輸出。
  15. The task in the paper comprises two parts. the software design procedure works as follow, program the drivers for module on pc with cvi, generate the corresponding ddl and then edit the test serial and invoke the ddl by designing soft panel with vc + + 6. 0. thus facilitate users to control module to conduct high speed data test. the hardware design procedure works as follow, design vxi message based interface circuit and plesio - fdc circuit with fast data transport function on xc2vp30, a virtex - ii pro series fpga chip designed by xilinx company which integrates power - pc processor

    筆者負責的工作包括軟體設計和硬體設計兩部分:軟體設計是用cvi工具編寫模塊在pc機上的驅動程序，生成動態連接庫，再用visualc + + 6 . 0設計軟面板，實現測試矢量的編輯和動態連接庫的調用，讓用戶很方便地控制模塊進行高速數據測試;硬體設計是在xilinx公司的一片集成了power - pc處理器的virtex - iipro系列fpga晶元xc2vp30上完成vxi總線的消息基介面電路設計和具有快速數據傳送功能的準fdc電路[ 1 ] [ 2 ]設計。
  16. Introduces operation principle and interface circuit design of video codec adv611. 3

    介紹了新一代視頻編解碼晶元adv611的工作原理和介面電路設計。
  17. The structure of the embedded controller the characteristic of the core chip the design of interface circuit the porting of uclinux os and the realization of embedded web server etc. are given in details

    主要包括：控制器硬體總體結構、核心晶元arm的介紹、介面電路設計、嵌入式控制器軟體設計中操作系統移植和服務程序的設計。
  18. Interface circuit chips

    介面電路晶元
  19. The hardware circuit and software of the portable copying instrument is researched. a feasible structure scheme is put forward according to the desired function, at89c51 single chip computer is used as the core of the instrument, zlg7289a and many kinds of new type circuit chip ( including : parallel data memory - ds1245, sms0823 lcd ) are used as interface during hardware circuit designing, the printer ' s port and rs232 communication interface is also designed

    硬體電路以at89c51單片機為核心，以zlg7289a按鍵組集成晶元作為人機介面，並採用新型電路晶元（包括大容量并行數據存儲器ds1245 、液晶顯示器sms0823 ）設計手持抄錄器的硬體電路，並設計了手持抄錄器的印表機介面和rs232通信介面，從而簡化了電路，減小了手持抄錄器的體積，按鍵的軟體實現過程。
  20. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
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