塊緩沖器 的英文怎麼說

中文拼音 [kuāihuǎnchōngqì]
塊緩沖器 英文
block buffer
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. The design of each functional module, including the bridge selected module, mlb slave state machine, buffer, ahb master state machine, arbiter. 4

    各功能模塊的設計，包括橋選擇單元、 mlb從狀態機、緩沖區、 ahb主狀態機，仲裁器； 4
  2. Through the implementing of kernel level file and cache mechanism at the client side, this newly proposed distributed network file system provides seamless network file access and reduces the performance decline caused by network transmission. utilizing the concept of logic block server, it provides the reliable data block storage and implements redundant storage capacity. utilizing the concept of the index server, it provide s the cost of the greatly for server and network during data access process and realizes the computing with balancing capacity

    在客戶端通過實現內核級文件的調用和緩沖機制，實現了文件的無縫網路存取，並減少由於網路傳輸帶來的性能下降的影響；利用邏輯塊服務器實現邏輯塊的冗餘存取，實現數據塊的安全存放；利用索引服務器進行負載均衡計算，實現資料存取的較低網路和服務器開銷；利用索引服務器實現服務器組的零管理，使該系統具有高效性、穩定性和可伸縮性。
  3. Cut current line or selected block to buffer

    剪切當前行或者所選代碼塊到緩沖器。
  4. It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks

    在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。
  5. Moreover, by choosing different kinds of write - back strategy, log management system can cooperate with buffer management to implement commit delay and group commit

    日誌管理模塊還通過對日誌回寫策略的調整，配合數據緩沖器進行延遲提交，成組提交，從而達到提高系統效率的目的。
  6. This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip, corresponding the mac sublayer of ethernet, to realize csma / cd media access protocol, manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface. 2 ) serdes ( serializing and deserializing ) chip, corresponding pcs and pma sublayers in ethernet, mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data, and convert them again at the receiving end. 3 ) fibre transceiver unit, completing light - electrical conversion of seri

    該網卡主要由3塊集成的晶元完成其功能，分別是i ）網路控制主晶元，對應于以太網的mac子層，主要完成csmaicd介質訪問協議，管理片上集成的發送和接收緩沖區，並提供和主板p0總線的介面： b ） s rd s （串列解串列化器）晶元，對應于以太同的pcs和pma子層，主要完成sb lob編碼並將10位并行的數據轉換為串列數據，在接收端完成相反的功能：涌）光纖收發器，完成串列數據的光電轉換功能。
  7. Research on cmos implementation of wlan transceiver rf front - end is done in this thesis. the transceiver uses the most used super - heterodyne architecture, its rf front - end consists of low noise amplifier, down - converter, up - converter, preamplifier, lo buffer and pll frequency synthesizer

    本論文研究無線局域網收發機射頻前端的cmos實現，該收發機採用超外差式的拓撲結構，其射頻前端主要由低噪聲放大器、下變頻器、上變頻器、末前級、本地振蕩信號緩沖器和鎖相環型頻率合成器等模塊組成。
  8. It contains two a / d channels, every channel has a 4kx 16bit buffer. it has three flexible trigger modes : inner trig, outer trig and software trig. vvp platform can support up to 4 plug - in boards ( 8 channel a / d ) to work together

    該模塊作為一塊vvp儀器平臺上的插板，採用20msps的16位a d轉換器，一塊插板上設計了2個高速a d轉換通道，每個通道有4k 16位的緩沖存儲器，可以內部觸發、外部觸發和軟體觸發。
  9. When a thread exits a synchronized block as part of releasing the associated monitor, the jmm requires that the local processor cache be flushed to main memory

    當線程為釋放相關監視器而退出一個同步塊時， jmm要求本地處理器緩沖刷新到主存中。
  10. The resource management also implements part of the jca1. 0 standard. thus, any eis system keeping to this standard can be easily added into istx1. 0. in addition, the resource management module combines with that of transaction processing, fulfilling the functions of resource enlist and delist in transaction managers

    Istx1 . 0中的資源管理模塊對系統中使用的所有數據庫進行了統一的連接緩沖和復用管理，有效提高了應用程序和istx1 . 0的性能；另外它對jca1 . 0規范進行了支持，任何遵循jca規范的eis系統都能方便地加入到istx1 . 0中；最後它和事務管理模塊結合在一起，共同實現了資源在事務管理器中的注冊和注銷功能。
  11. In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  12. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same

    分支目標緩沖器會查出是否有預測會發生的分支指令跨過多個快取區塊，則讀取位址會指到下一個快取區塊而搜尋位址則會保持不變。
  13. File - blocks cache ? when a file is opened, the kernel checks with the remote server whether to fetch or revalidate the cached attributes

    文件塊緩存-當一個文件被打開時，內核與遠程服務器一起檢查是否取或重新設置緩沖的屬性。
  14. The production is composed of dtzziii - ah type elevator weight - load indicating controller box, four pressure sensors and buffer rubbers

    產品由dtzz - ah型電梯重量載荷指示控制儀四隻壓力傳感器和緩沖橡膠塊組成。
  15. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
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