指令周期時間 的英文怎麼說

中文拼音 [zhǐlìngzhōuqīshíjiān]
指令周期時間 英文
instruction cycle time
  • 指 : 指構詞成分。
  • 周 : Ⅰ名詞1 （圈子; 周圍） circumference; periphery; circuit 2 （星期） week 3 [電學] （周波的簡稱） c...
  • 期 : 期名詞[書面語]1. （一周年） a full year; anniversary 2. （一整月） a full month
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 間 : 間Ⅰ名詞1 （中間） between; among 2 （一定的空間或時間里） with a definite time or space 3 （一間...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 時間 : time; hour; 北京時間十九點整19 hours beijing time; 上課時間school hours; 時間與空間 time and spac...
  1. As a result of studying, we gain three system time capability parameter of monolayer bus framework and two - double bus framework, data bus utilization, length of the data waiting queue and time of system timed, basing on fixed bc control seasonal repertoire timed petri net and stochastic petri net

    研究結果分別得出了單總線和雙總線的基於固定主控端周期指令時延petri網的數據總線利用率、等候消息隊長、系統延時時間；基於隨機petri網的數據總線利用率、等候消息隊長、系統延時時間共三個系統時間性能指標。
  2. There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost

    從消除信號阻塞到進程執行下一個指令之間，必然會有時鐘周期間隙，任何在此時間窗口發生的信號都會丟掉。
  3. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  4. And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper

    為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間，又要達到單周期完成一條運算指令的吞吐量指標，本文提出對ex級進行可伸縮超流水擴展的思想，提出並實現了一種高性加比的切換控制方案。
  5. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼，以及多時鐘同步的控制流設計方法；進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
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