控制緩存器 的英文怎麼說

中文拼音 [kòngzhìhuǎncúnqì]
控制緩存器 英文
control registei
  • 控 : 動詞1 （告發;控告） accuse; charge 2 （控制） control; dominate 3 （使容器口兒朝下 讓裏面的液體慢...
  • 制 : Ⅰ動詞1 （製造） make; manufacture 2 （擬訂; 規定） draw up; establish 3 （用強力約束; 限定; 管束...
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 控制 : control; dominate; regulate; govern; manage; check; cybernate; manipulate; encraty; rule; rein; c...
  • 緩存 : buffer
  1. This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches

    本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。
  2. Secondly, the paper describe the principle of atm network, and the function of ' sar " ( segmentation and reassembly ) and the format of packet aal5, and introduce the basic idea of ipoa, and the design project and implementing of the control chip. later, the paper introduce the logic function and operational principle of packet buffer control chip and prove the feasibity and correctness of the arithmetic. at last the paper introduce crc - 32 arithmetic based on look up and implement it with hardware

    接著詳細論述了核心路由器atm網路實現的原理，包括「 sar 」 （ segmentationandreassembly ）功能和aal5報文的格式， ipoa基本思想，以及控制晶元的設計方案和實現途徑等。然後又論述報文緩存區控制晶元的工作原理和邏輯功能等，並對演算法的可行性，正確性等進行論證。最後介紹了一種基於查表的crc - 32演算法的原理及其硬體實現。
  3. A data acquisition system with the following features is realized : ? transmission rate up to 100kbyte / s over usb ; ? system ' s dynamic range as high as 120 db ; ? multi - kind of trigger mode control ; ? sampling rate as high as 100 ksps ; ? 12 - bit a / d conversion accuracy ; ? 32k bytes on - board data memory ; ? the system, which was made up of large - scale electronic chips, is small, light and portable, and suitable for field use

    本設計最終實現了一個瞬態信號數據採集系統，它具有以下特點： ?採用usb介面進行高速數據傳輸，傳輸速度達100kbyte / s ； ?採用浮點a / d轉換技術，動態范圍達120db ； ?多種采樣觸發控制方式； ?最高采樣率100ksps ； ? 12位采樣精度： ? 32kb數據緩存； ?使用新型大規模電子器件，系統結構緊湊，重量輕，適合野外作業。
  4. In the third chapter, the hardware design of the radar echo simulator is introduced, including the unitary chart of hardware structure and design of each part in this system, which is composed of designs of computer interface, controlling sdram and controlling ide harddisks and some introduction about d / a and fpgas used in this system

    再次，介紹了本雷達回波模擬器的硬體設計，包括總體硬體結構框圖、系統各部分的硬體設計。系統各部分的硬體設計包括計算機介面設計、大容量高速緩存sdram的控制設計、 ide介面硬盤的控制設計、關于d / a的介紹和本系統使用的fpga的介紹。
  5. A new bit rate control strategy with both global pre - allocation and local segmentation ( glas ) for low bit rate application is proposed. first, it allots bit date to every frame in advance according to possessive rate of buffer, and then distribute different quantization parameters according conctete detail. by means of this method, buffer is controlled more particularly. and the quality of decoded image is improved, the traditional video image coding method, that is to say, the intraframe coding based on dct and the interframe prediction coding based on motion compensation, is not suitable for low bit rate compression and aside from this, the encoder is too complicated

    它首先在總體上根據緩存器的佔有率給每幀預分配比特數，然後再根據具體細節給予不同的量化參數。使緩存器得到了更細致的控制，解碼圖像的質量有所改善。針對傳統的視頻圖像編碼方法，即幀內基於dct的編碼加幀間基於運動補償的預測編碼存在不適于低比特率壓縮，編碼器復雜等不足，討論了基於3 - ddct的xyz視頻圖像壓縮編碼方法，提出了3 - ddct系數的三維「 z 」形掃描方案，大大提高了編碼效率。
  6. The high - speed data buffer is designed by adopting cpld and general high - speed static memory. 5

    採用cpld控制邏輯外加通用靜態高速存儲器來實現採集后數據的高速緩存。
  7. It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks

    在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。
  8. Forces cached domain controller data to be ignored when searching for domain controllers

    當搜索域控制器時，將強制忽略緩存的域控制器數據。
  9. The evaluation method of element in state transition matrix is given when the wrong order of data packet is considered. considering the wrong order of data packets, the mathematic model of networked control systems with long time delay is developed. the sufficient and necessary conditions for stochastic stability of such networked control systems with long time delay are given

    分析了長時延網路控制系統的二階矩穩定性和隨機穩定性；針對網路傳輸中的數據包的時序錯亂問題，提出了第二緩沖器的方法；分析了網路誘導時延的markov特性，並給出了時延markov鏈的狀態轉移矩陣中元素的求取方法；建立了存在數據包時序錯亂時長時延ncs的數學模型，並給出了對應的長時延ncs隨機穩定的充分必要條件。
  10. The. net framework version 2. 0 improves scalability and performance of applications with improved caching, application deployment and updating with clickonce, support for the broadest array of browsers and devices with asp. net 2. 0 controls and services

    . net framework 2 . 0版改進了緩存，從而提高了應用程序的可擴展性和性能使用clickonce改進了應用程序部署和更新通過asp . net 2 . 0控制項和服務對各種瀏覽器和設備提供更強大的支持。
  11. Microcontroller working registers

    微控制器工作緩存器
  12. All cards contain one or more lan or wan ports ; a forwarding table, which is a simplified version of the full route table ; the qbrt hardware ; packet - forwarding hardware ; buffering capacity ; and separate interfaces to the route manager and the switch engine on the control board

    所有卡都包括：一個或多個局域網或廣域網埠、一個轉發表（即完整路由表的簡化版） 、 qbrt硬體、包轉發硬體、緩存容量以與控制板上路由管理器和開關引擎獨立的介面。
  13. And it has been integrated in a prototype chip which is fabricated with tsmc 0. 18 - um cmos technology, and the experimental results show that this architecture can achieve the real time avs - p2 decoding for the hdtv 1080i 1920 1088 4 : 2 : 0 60field s video. the efficient design can work at the frequency of 148. 5mhz and the total gate count is about 225k

    為支持直接模式預測，該模塊通過一個fifo來實現p圖像下mv緩存和b圖像下mv預取的功能，以突發方式來進行訪存操作，從而避免了頻繁而瑣碎的訪存請求，使外存控制器能夠更好地為其他訪存模塊服務。
  14. Enterprise information system framework provides a series of reusable groupware, such as persistence layer which introduces dynamic value object 、 value list hander and command pattern, it encapsulates the detail of accessing database and affords the interface of different persistence layer framework ; basing on asynchronous javascript and xml ( ajax for short ), we develops the client validity check engine 、 dynamic cascading menu and common 、 dynamic tree structure groupware, as well as a set of tag library which include query 、 pagination 、 cache an so on. they reduce the code redundancy and predigests the development of interface layer enormously ; the security subsystem which is based on secure socket layer ( ssl for short ) and role - based access control ( rbac for short ) ensures the data security transmission and privilege control. furthermore, the model of enterprise application integration ( eai for short ) which based on web services, it supply some helpful explore for the sake of system integration and data communion for the future

    企業信息系統框架提供了一系列可復用組件，例如採用動態vo 、值列表處理器以及命令模式的持久層組件，封裝了數據庫訪問細節，並為不同的持久層框架提供調用介面;基於ajax （ asynchronousjavascriptandxml ）技術的客戶端校驗引擎、動態級聯菜單以及通用動態樹型結構組件，一系列查詢、分頁、緩存等標簽庫則減少了表示層的代碼冗餘，簡化了表示層開發;基於ssl登錄以及基於角色的訪問控制的安全子系統則初步實現了數據安全傳輸和權限控制;此外基於web服務的企業應用集成模型為今後系統集成、數據共享提供了有益探索。
  15. In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  16. Server control implements support for post - cache substitution internally

    服務器控制項在內部實現對緩存后替換的支持。
  17. It uses omnivision ' s cmos digital color image sensor ov7620 sampling the object image, ti ' s tms320vc5409 dsp as main controller, icsi ' s high speed sdram ic42s16100 as data buffer, altera ' s flex10k series cpld designing sdram interface and time sequence logic

    採用了omnivision公司的cmos數字彩色攝像晶元0v7620采樣物體圖像， titms320vc5409dsp作為主控制器， icsi的高速sdramic42s16100為數據緩存， alteraflex10k系列cpld來設計sdram介面和時序邏輯。
  18. After briefly introduce the basic genetic algorithm ( ga ) theory, aimming at the " prematurity " of basic genetic algorithm, we put forward a new improved genetic algorithm, the basic genetic algorithm combine simulate anneal ing ( gasa ), to meliorate the local search ability of basic genetic algorithm. because many design problems, such as the preliminary fuzzy rule and input and output membership fuction are hard to gain and the learni ng process of fuzzy neural network ( fnn ) is slow and local optimization, we design the fuzzy neural network excitation controllers of turbine generators with genetic algorithm combine simulate anneal ing ( gasa )

    本文首先介紹了水輪發電機勵磁控制方式和軟計算理論的發展，然後介紹了遺傳演算法的基本理論，針對基本遺傳演算法存在的「早熟」現象，介紹了一種遺傳演算法結合模擬退火的改進型遺傳演算法，改善了基本遺傳演算法的局部搜索能力。鑒于常規模糊神經神經網路勵磁控制器設計方法中存在著初始模糊規則和輸入輸出隸屬度函數難以確定以及模糊神經網路訓練緩慢和難以達到全局最優等問題，利用遺傳演算法結合模擬退火的改進型遺傳演算法來設計模糊神經網路勵磁控制器。
  19. The hardvvare consists of a / d converter, first in first out buffers, programmable logic device and pci bus controller s5933. the softvvare consists of hardware driver and application program

    系統硬體部分主要包括md轉換、先進先出數據緩存器、控制讀寫邏輯的可編程邏輯器件和pci總線介面晶元s5933 ，軟體部分即數據採集卡的驅動程序和應用程序。
  20. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
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