控制邏輯部件 的英文怎麼說

中文拼音 [kòngzhìluóbùjiàn]
控制邏輯部件 英文
control logic unit
  • 控 : 動詞1 （告發;控告） accuse; charge 2 （控制） control; dominate 3 （使容器口兒朝下 讓裏面的液體慢...
  • 制 : Ⅰ動詞1 （製造） make; manufacture 2 （擬訂; 規定） draw up; establish 3 （用強力約束; 限定; 管束...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 部 : Ⅰ名詞1 （部分; 部位） part; section; division; region 2 （部門; 機關或組織單位的名稱） unit; mini...
  • 件 : Ⅰ量詞（用於個體事物） piece; article; item Ⅱ名詞1. （指可以一一計算的事物） 2. （文件） letter; correspondence; paper; document
  • 控制 : control; dominate; regulate; govern; manage; check; cybernate; manipulate; encraty; rule; rein; c...
  • 邏輯 : logic
  • 部件 : component; unit; parts; assembly; subsystem; secundina （pl. secundinae）
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. The area within the field of fluidics in which components and systems perform functions such as sensing, logic, amplification, and control without the use of mechanical parts

    射流技術的一個領域，其部件和系統執行諸如傳感、邏輯、放大和控制之類的功能，而不使用機械零件。
  3. The dcs of i / a series is regarded as main reference object, and the control is separated from model. and the configuration of control is operatised at administration system, not to be added into model, not to build control sound code also. therefore it realizes on - line adjusting, real - time control and so on. users configurate by filling table. they only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, so personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the system, not need to know the programs deeply. so the configuration software offer a flat that control engineers can attend to control loop, not to give their attention to the complicated program

    在本課題中，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對系統的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  4. This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis. and it is a part of control flow synthesis in a controller synthesis system. in this paper following problems are proposed and implemented : ( 1 ) implement the algorithm " espresso ", and make it suit to the system

    本文所完成的組合邏輯綜合的研究與實現是控制流綜合系統的一個組成部分，其中包括： （ 1 ）引入並實現了兩級邏輯綜合的「 espresso 」演算法，定義與系統相適應的數據結構，重新測試各種開關條件，使之適用於系統的實際應用。
  5. Therefore it comes true the on - line adjusting, real - time control and so on. it sames as real locale. the software of logic protect ( include electric logic ) and control includes some usual algebraic and operation model of thermal control and logic operation of logic protect. it adopts foxboro ' s dcs as a example, so we configuration via filling table, user only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the set, not need to know about the inside of the old programs deeply. so the configuration software offer a flat that control engineer can attend to the structure of control loop and logic protect ( include electric logic ), not but to handle complicated program

    它以foxboro的dcs控制系統為主要參考模式，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名、邏輯變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對機組的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路及邏輯保護（包含電氣邏輯）的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  6. A processor is composed of two functional units ? a control unit and an arithmetic / logic unit ? and a set of special workspaces called registers

    處理器由兩個功能部件（控制部件和算術邏輯部件）與一組稱為寄存器的特殊工作空間組成。
  7. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  8. 1. a small and cheap 8 - bit microcontroller is used as control core. all components of the sensor, some of which are necessary for the multiple and intelligent functions, are selected ones with low cost and small package. by designing all auxiliary logic circuits in a complex programmable logic device ( cpld ), and integrating all analog circuits in an application specific ic ( asic ), the size of pcb board is greatly reduced, which make it possible that the pcb can be installed with the displacement detector together

    系統採用小型廉價8位微控制器控制，電路內配置了為實現多功能智能化所必需的硬體，並全部採用低價格、小體積器件，還將所有輔助邏輯電路設計在一片復雜可編程邏輯器件cpld內，所有模擬電路集成於一片專用集成電路asic內，大大縮小了電路板尺寸，再與傳感元件組裝在一起，從而使整個系統在保證智能化功能的前提下，具有體積小、成本低、一體化和抗干擾能力強的特點。
  9. As part of this process, find a component listed on one or both of these hcls as incompatible with linux

    同樣地這一程序的一部份，找被列出的一個元件在一之上或這兩個字錘控制邏輯當做不相容的與linux 。
  10. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  11. The control system includes two modules, one named the input module which acquires data digitally, and the other, named the output module, controls the emission of the laser, the gating function of the single photon counting module ( spcm ) and the synchronization of the input and output modules. each of them uses a complex programmable logic device ( cpld ) as the core component, and is devided into three parts : the hardware circuit, the programming logic circuit and the software

    該控制系統主要包括控制單光子發射、單光子探測器、數據採集接收系統的輸出系統和數據採集系統兩個模塊，它們都採用復雜可編程邏輯器件cpld作為核心功能晶元，由硬體電路設計、晶元編程和高級軟體編程三部分組成。
  12. As to the software, we firstly scheduled all of the test signal path between the computer and the uut, the output control logic between the digital i / o card and programmable relay key matrix, and used all of this to be the base of software design, then we introduce the block flow of software

    在軟體設計部分首先規劃了所有測試信號在計算機主機與被測件之間的連接和傳輸路徑、數字i / o卡對可編程繼電器開關矩陣的輸出控制邏輯，作為軟體設計依據，隨后介紹了軟體的模塊化設計思想。
  13. Last, the cpld / fpga can load difference hdl. so the control logic can be change easily. i use fuzzy control to make the control character better

    最後，利用可編程邏輯器件的靈活性，載入不同的硬體描述程序改變內部邏輯電路，實現不同的控制邏輯。
  14. The emphasis of this article is the design in the second period, which is based on the pic microchip interface, because at present embedded structure is adopted by most of medical instruments so that it can run separately without computer, hi this part the article specifically introduces the interface circuit of pic16f877 single - chip, which includes the acquisition of a / d signa ls and the serial communication between the single - chip and computer, the design of complex programmable logic device ( cpld ) and the using of hardware describe language ( vhdl ) to control the rotate speed of 4 - route stepping motors

    本論文的重點是在設備的第二階段開發，它是基於pic系列單片機介面的硬體設計，主要是針對現階段大多數醫療設備都是採用嵌入式結構，它能夠脫離計算機單獨運行。在這部分詳細介紹了pic16f877單片機的外圍電路，包括a d信號的採集、單片機與計算機的串列通信，可編程邏輯器件cpld硬體的設計，以及用硬體描述語言vhdl編程來同時實現4路步進電機的轉速控制。
  15. Based on the hardware architecture of ivtds, are discussed in detail the component units of the system which are image data acquisition unit, data pre - processing unit and logical control etc. the design of the fpga function and its implementation are carried on vhdl language and top - down method

    還在介紹紅外運動目標檢測與跟蹤系統組成的基礎上，詳細討論了圖像數據採集部分的結構，圖像數據的預處理， dsp與fpga之間的通訊和fpga對其他器件的控制邏輯等。
  16. In this paper, the principle and method that making use of complex programmable logic devices ( cpld ) to realize high accurate pwm controller are chiefly analyzed, and a new control method and amendatory strategy for the triple multi - level convector based on cpld is put forward. by carefully analyzing the triple multi - level power amplifier composed of four bridges converter bridge, the fact and idea that complex programmable logic devices ( cpld ) have high speed

    本文詳細討論分析了用可編程邏輯器件cpld實現高精度pwm控制器的原理和方法，並且提出了一種基於cpld器件的三進制多電平逆變器的控制方法和改進策略，針對具有四級逆變橋結構的三進制多電平功率放大器進行了具體的分析和驗證，證實了可編程邏輯器件內部高速處理的性能和在電力電子技術控制中的應用優勢。
  17. Fluid - power systems and components. fluid logic circuit. part 1 : symbols for binary logic and related functions

    液壓動力系統和元件.液控邏輯電路.第1部分:二進制邏輯及有關功能符號
  18. This paper projects a utility subdividing drive system of step motor, which consists of digital control module, drive module and power module, it uses at89c52 single chip processor as the core, it realizes the external event or generates control signal by i / o interface, timer and external interruption, the system introduce pld device and isp technology to the design of phase sequencer, it simplified circuit and improved the anti - disturbing capability by using abel - hdl language, this system can realizes data memory, velocity digital control and led display, etc. this paper adopted firstly the single - chip technique to design control system, which replaced old complicated logic control circuit and simplified test process

    本文研究了一種實用的步進電機細分驅動系統，由數字控制模塊、驅動模塊和電源模塊組成，系統以at89c52單片機為核心，通過單片機的i o口、定時器計數器中斷來實現外部事件監控以及控制信號的產生，系統將可編程邏輯器件（ pld ）器件和在系統編程（ isp ）新技術引入到細分驅動環行分配器的設計，通過abel _ hdl語言編程實現硬體軟化設計和邏輯重構，大大簡化了電路，並提高了電路抗干擾能力。使系統實現參數存儲，速度數字控制，數碼顯示，進退刀控制等功能。
  19. The hardvvare consists of a / d converter, first in first out buffers, programmable logic device and pci bus controller s5933. the softvvare consists of hardware driver and application program

    系統硬體部分主要包括md轉換、先進先出數據緩存器、控制讀寫邏輯的可編程邏輯器件和pci總線介面晶元s5933 ，軟體部分即數據採集卡的驅動程序和應用程序。
  20. In addition to these, the most important chips are cpld which can be upgrated and expanded easily, which makes it possible that the capability can be optimized and the operation can be expanded without changing the hardware. the type of the bus controlling based on the cpld ensures the operatings are processed in the same pri, and then it can let another chips deal with the processing when some chip can not afford

    保證的對信號和業務處理能力，而且關鍵晶元均採用可編程邏輯器件，有較強的升級和擴張能力，可以保證硬體不改變的情況下進行性能優化和業務擴展。基於cpld的總線控制方式也可以實現業務功能的均勻分擔，可部分實現某些晶元處理性能不夠的情況下講部分處理業務分擔至其他晶元。
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