掩模製造 的英文怎麼說
中文拼音 [yǎnmózhìzào]
掩模製造
英文
mask making-
Developing the lithography process models to properly characterize critical dimension ( cd ) variations caused by proximity effects and distortions introduced by patterning tool, reticule, resist exposure, development and etching, they are beneficial to develop a yield - driven layout design tool, the engineers could use it to automate the tasks of advanced mask design, verification and inspection in deep sub - micron semiconductor manufacturing
建立準確描述由於掩模製造工藝、光刻膠曝光、顯影、蝕刻所引起的光學鄰近效應和畸變所導致的關鍵尺寸變化的光刻工藝模型，有助於開發由成品率驅動的版圖設計工具，自動地實現深亞微米下半導體製造中先進的掩模設計、驗證和檢查等任務。The second is about verification of alternating psm manufacturability and this part introduces a new method based on standard cells to resolve the phase conflicts, including for dark field and for clear field. the method has the capabilities of verifying standard cell layout, locating features with phase conflicts and giving out suggestion for modification
第二部分針對由傳統方法設計出的版圖不能滿足交替移相掩模要求的問題，介紹了一種基於標準單元的交替移相掩模可製造性驗證與設計的演算法，包括針對暗場和亮場兩種不同環境版圖的演算法。Lithography, as used in the manufacture of ics, is the process of transferring geometic shapes on a mask to the surface of a silicon wafer.
光刻技術應用到集成電路製造中，就是將掩模版的幾何圖形轉移到矽片表面的工藝過程。Before more advanced lithography tool is produced, in order to use current tools to manufacture vdsm ic, reticle correction methods such as perturbing the shape ( via optical proximity correction ( opc ) ) or the phase ( via phase - shifting masks ( psm ) ) of transmitting aperture in the reticle are proposed by the industry
在波長更小的光刻系統出現前，為了能利用現有設備解決集成電路的可製造性問題，工業界提出了對掩模作預失真（光學鄰近校正）和在掩模上加相位轉移模（移相掩模）等的掩模校正方法。The paper is for verification and design of manufacturability of opc and psm as these two ways have become the most important correction ways
由於光學鄰近校正和交替移相掩模已經成為最主要的掩模校正方法，因此本文主要針對這兩種方法進行可製造性的驗證和設計。However, in current design flow, designers do not consider whether designs are friendly to opc before they are sent to foundries. in fact, a lot of features in such designs can not be corrected enough because of many factors such as the constraints of environments. so even though such designs are corrected, many lithographic errors still exist
然而，由於在當前的集成電路設計流中，在設計出的版圖送到製造廠商前，電路的設計者並沒有考慮版圖對光學鄰近校正和交替移相掩模的友好性問題，這使得版圖中的一些圖形由於周圍條件的限制，如無法充分進行光學鄰近校正，無法進行交替移相掩模的處理等，從而使得版圖設計即使進行了校正處理，還存在大量光刻故障的可能性。分享友人